Method of fabricating a MOS transistor in an embedded memory

Details Method of fabricating a MOS transistor in an embedded memory Method of fabricating a MOS transistor in an embedded memory

2001-03-29

2002-05-28

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000

Reexamination Certificate

active

06395596

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method of fabricating a MOS transistor in an embedded memory, more particularly, a method of simultaneously forming a periphery circuit region and a memory array area in the embedded memory of the MOS transistor.
2. Description of the Prior Art
Due to the rising integration density of semiconductor processes, the trend has been to integrate both a memory cell array and high-speed logic circuit elements onto a single chip to form an embedded memory. As a result, both a decrease in area occupation and an increase in signalling speed are achieved. The high-speed logic circuit elements mentioned are also referred to as the periphery circuit region. Because of demand for low resistance and high-speed speed MOS transistors formed in the periphery circuits region, a self-alignment silicide (salicide) process is commonly used in the semiconductor process to form a silicide on the surfaces of a gate, source and drain of each MOS transistor in the periphery circuits region. As a result, the interface resistance on the surfaces of the gate, source and drain in each MOS transistor is decreased.
As well, the self-aligned-contact (SAC) process is used to solve the electrical connection problem of the memory cell in the memory array area, whereby a cap layer and a spacer, both composed of silicon nitride, are formed on the sidewall and on the surface of the gate of the pass transistor in the memory array area to function as an isolation mask needed in the subsequent SAC process. Therefore, the problem of the prior art results in the inability to simultaneously perform both the above processes to save production time.
In addition, the spacing between each gate in the memory array area is of closer proximity than in the periphery circuit region, so that the spacer adjacent to each gate in the memory array area is of lesser thickness in order to avoid producing voids in the dielectric layer that fills the area between the word lines. Oppositely, due to electrical requirement, the width of the spacer in the MOS transistor formed in the periphery circuits area is not able to be so close as in the memory array area to let the problems of the integration of both processes happen.
Please refer to
FIG. 1
to FIG.
9
.
FIG. 1
to
FIG. 9
are the schematic diagrams of fabricating a MOS transistor on semiconductor wafer
10
of an embedded memory according to the prior art. As shown in
FIG. 1
, both the memory array area
12
and a periphery circuits area
14
are defined on the surface of a silicon substrate
16
on the semiconductor wafer
10
. Several trenches
11
separate each area. A dielectric layer
18
, a polysilicon layer
20
, and an etching barrier layer
22
are formed, respectively, on the surface of the semiconductor wafer
10
. And then shown in
FIG. 2
, a mask layer
24
is formed on the etching barrier layer
22
in the periphery circuits area
14
, followed by the use of an isotropic wet etching process to simultaneously remove both the etching barrier layer
22
and the polysilicon layer
20
in the memory array area
12
, down to the surface of the dielectric layer
18
.
As shown in
FIG. 3
, the mask layer
24
on the etching barrier layer
22
is then removed, followed by the removal of the dielectric layer
18
in the memory array area
12
to expose the surface of the silicon substrate
16
. As shown in
FIG. 4
, a dielectric layer
26
functioning as a gate oxide layer is formed on the surface of the exposed silicon base in the memory array area
12
. Next, a polysilicon layer
28
, a tungsten silicide layer
30
, and a silicon nitride layer
32
are formed, respectively, on the surface of the semiconductor wafer
10
.
As shown in
FIG. 5
, a photoresist layer
34
is formed on the silicon nitride layer
32
and the patterns of the gates in both the memory array area
12
and the periphery circuits area
14
are defined by a PEP. Then, the silicon nitride layer
32
, the tungsten silicide layer
30
, and the polysilicon layer
28
are etched down to the surface of the dielectric layer
26
in the memory array area
12
by using the patterns of the photoresist layer
34
as a hard mask. Concurrently, the silicon nitride layer
32
, the tungsten silicide layer
30
, and the polysilicon layer
28
are etched down to the surface of the etching barrier layer
22
in-the periphery circuits area
14
. As shown in
FIG. 6
, another photoresist layer
36
is formed in the memory array area
12
after the photoresist layer
34
is removed to cover and protect the gate structure
33
composed of the dielectric layer
26
, the polysilicon layer
28
, the tungsten silicide layer
30
and the silicon nitride layer
32
in the memory array area
12
.
As shown in
FIG. 7
, the photoresist layer
36
in the memory array area and the silicon nitride layer
32
in the periphery circuits area
14
are used as hard masks, to etch both the etching barrier layer
22
and the polysilicon
20
down to the surface of the dielectric layer
18
to form the gate
35
structure in the periphery circuits area
14
. Next, the silicon nitride layer
32
, the tungsten silicide layer
30
, the polysilicon layer
28
and the photoresist layer
36
are removed.
As shown in
FIG. 8
, lightly doped drains (LDD)
38
in each MOS transistor are formed by performing an ion implantation process. Next, a silicon nitride layer
43
is deposited on the surface of the semiconductor wafer
10
, and a spacer
44
is formed on either side of the gate
35
in the periphery circuits area
14
using an anisotropic etching process, and simultaneously, the etching barrier layer
22
on the gate
35
is removed. Then, a source
40
and drain
42
of each MOS transistor are formed in the periphery circuits area
14
. Finally, as shown in
FIG. 9
, a salicide layer
46
is formed on the surface of each source
40
, drain
42
and gate
35
using a self-aligned silicide process in the periphery circuits area
14
.
However, the prior art method of fabricating a MOS transistor involves a step, as shown in
FIG. 7
, of removing the silicon nitride layer
32
in the periphery circuits area
14
because the silicon nitride layer
32
is not required in the formation of the gate
35
in the periphery circuits area
14
. As well, the spacer
44
in the periphery circuits area
14
shown in
FIG. 8
is unable to attain a large enough spacer width to achieve the desired electrical performance.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method of fabricating a MOS transistor in an embedded memory to solve the above-mentioned problems.
In the present invention, a first dielectric layer, an undoped polysilicon layer, and a second dielectric layer are formed, respectively, in both the memory array area and in the periphery circuits area on the surface of a semiconductor wafer. Next, a doped polysilicon layer is formed by doping the undoped polysilicon layer in the memory array area followed by the removal of the second dielectric layer in the memory array area. Then, both a silicide layer and a protective layer are formed, respectively, on the surface of the semiconductor wafer. The protective layer, the silicide layer and the doped polysilicon layer in the memory array area are then etched to form a plurality of gates, and the protective layer and the silicide layer in the periphery circuits area are etched in-situ. Thereafter, lightly doped drains (LDD) of the MOS transistor in the memory array area are formed. Next a portion of the undoped polysilicon layer in the periphery circuits area is etched to form a plurality of gates, followed by the formation of LDDs of each MOS transistor in the periphery circuits area. Then, a silicon nitride layer and acompensated silicon oxide layer are formed, respectively, on the surface of the semiconductor wafer. A portion of the silicon nitride layer and the compensated silicon oxide layer in the periphery circuits area are then etched to form a spacer on either side of

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