Method of forming CMOS integrated circuitry

Details Method of forming CMOS integrated circuitry Method of forming CMOS integrated circuitry

2001-04-10

2002-03-19

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S232000, C438S275000, C438S305000, C438S307000

Reexamination Certificate

active

06358787

ABSTRACT:

TECHNICAL FIELD
This invention relates to methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry, and to methods of forming field effect transistors.
BACKGROUND OF THE INVENTION
An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers.
CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.
NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.
CMOS fabrication does however present a number of challenges to the fabricator as compared to using PMOS or NMOS alone. Specifically, typically independent or separate masking steps are utilized for masking one of the p-type regions while the n-type region is being doped. Also, the n-type regions are separately masked when the p-type regions are being doped. Accordingly, typical transistor flows use one mask each to form the n-channel and p-channel transistor source and drain regions. Higher levels of integration result in denser and denser circuits, leading CMOS fabrication to more difficulties.
It would be desirable to develop methods which further facilitate formation of complementary source and drain regions within a semiconductor substrate.


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