Transmission lines for CMOS integrated circuits

Details Transmission lines for CMOS integrated circuits Transmission lines for CMOS integrated circuits

1999-07-30

2002-04-16

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Format or disposition of elements

C333S238000, C333S246000

Reexamination Certificate

active

06373740

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly, to a method and structure for providing novel transmission lines for CMOS integrated circuits.
BACKGROUND OF THE INVENTION
As clocking systems and switching speeds on integrated circuits progress into the GigaHertz (GHz) range and beyond, chip interconnects become more and more critical. Signal delays on transmission lines terminated in their characteristic impedance are of the order of 70 picoseconds per centimeter (ps/cm) when oxide insulators are used. Long signal connections and clock distribution lines operating in the GHz range require the use of low impedance terminated transmission lines for good signal quality and controlled timing skews. These controlled and low impedance lines may not only be terminated at the receiving end by matching impedance but low output impedance drivers may also be used to provide a matching impedance at the sending end of the line.
FIGS. 1A-1C
show the classical types of high frequency transmission lines used in microwave, hybrid and printed board circuits for signal interconnections and clock distribution. In
FIG. 1A
, a coaxial line for use in connecting electronic circuits is illustrated. In particular,
FIG. 1A
includes a transmission line
102
that is enclosed by an insulator material
104
which in turn is enclosed by a conductive material
106
. Additionally, because power supply ringing and substrate bounce are becoming so problematic, metal power supply and ground planes have been incorporated into these types of circuits.
FIG. 1B
illustrates the incorporation of these power supply and ground planes. Specifically,
FIG. 1B
includes an insulator material
108
. Power supply or ground planes
112
A and
112
B are deposited on the insulator material
108
. Additionally, a transmission line
110
is deposited on the insulator material
108
in between the power supply or ground planes
112
A and
112
B. The incorporation of these planes reduces power supply transients and bounce associated with inductive and resistive voltage drops in the power supply bus. Similarly, a conductive ground plane, as shown in
FIG. 1C
, can be used to reduce ground bounce and transient-voltages. In particular,
FIG. 1C
includes a ground plane
114
A and an insulator material
116
deposited on the ground plane
114
A.
FIG. 1C
also includes a transmission line
118
located within the insulator material
116
. Additionally, a ground plane
114
B is deposited on the insulator material
116
. These techniques have resolved problems associated with high frequency transmission lines for microwave, hybrid and printed board circuits. Still, there is a need to provide a solution for these types of problems for CMOS-scaled integrated circuits. Due to the continued reduction in scaling and increases in frequency for transmission lines in integrated circuits such solutions remain a difficult hurdle. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above mentioned problems with transmission lines in CMOS integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are described which accord improved benefits.
Improved methods and structures are provided for impedance-controlled low-loss transmission lines in CMOS integrated circuits. The present invention offers a reduction in signal delay. Moreover, the present invention further provides a reduction in skew and crosstalk. Embodiments of the present invention also provide the fabrication of improved transmission lines for silicon-based integrated circuits using conventional CMOS fabrication techniques.
Embodiments of a method for forming transmission lines in an integrated circuit include forming a first layer of electrically conductive material on a substrate. A first layer of insulating material is then formed on the first layer of electrically conductive material. The method also includes forming a pair of electrically conductive lines on the first layer of insulating material. Moreover, a transmission line is also formed on the first layer of insulating material. In particular, the transmission line is formed between and parallel with the pair of electrically conductive lines. The method also includes forming a second layer of insulating material on both the transmission line and the pair of electrically conductive lines. A second layer of electrically conductive material is then formed on the second layer of insulating material.
One method of the present invention provides transmission lines in an integrated circuit. Another method includes forming transmission lines in a memory device. The present invention includes a transmission line circuit, a differential line circuit, a twisted pair circuit as well as systems incorporating these different circuits all formed according to the methods provided in this application.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.


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