Method of forming a mixed-signal circuit embedded NROM...

Details Method of forming a mixed-signal circuit embedded NROM... Method of forming a mixed-signal circuit embedded NROM...

2001-07-26

2002-08-27

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000

Reexamination Certificate

active

06440798

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a system on chip(SOC),and more particularly, to a method of forming a mixed-signal circuit system on chip embedded with nitride read only memory(NROM) and mask read only memory(MROM). The read only memory is formed by ROM coding a portion of nitride read only memory.
2. Description of the Prior Art
Recently, due to the increasing requirement of low energy consumption and PC-embedded consumer information apparatus” (IA), together with the upgrading of semiconductor manufacturing techniques, the design of system on chip(SOC) has become a trend. System on chip integrates and manufactures conventional and various chip units, such as central processing unit(CPU), micro controller unit(MCU), memory, periphery circuit, mixed signal circuit, digital signal processor(DSP), and network IC in a single chip. The advantage of system on chip includes higher efficiency, better reliability and lower cost.
In U.S. Pat. No. 5,403,764, Yamamoto et al. proposes a method of flash ROM embedded with read only memory. Yamamoto utilizes two ion implantation processes to implant dopant into the silicon substrate in the read only memory area in order to alter the threshold voltage of read only memory. After completion of writing “0” and “1” into the read only memory, the conventional flash ROM manufacturing process, such as floating gate, inter-poly insulating layer and control gate, is performed.
Please refer to
FIG. 1
to
FIG. 4
, of the method Yamamoto et al. proposes comprising the following steps: (a). Form an isolation layer
4
on a substrate
1
; (b). Form field oxide layers
8
in order to isolate each memory cell; (c). Form a dopant area
10
in order to write in “1” in the read only memory; (d). Form a dopant area
11
in order to write in “0” in predetermined address. (e). Form a floating gate
5
, inter-poly insulating layer
6
and a control gate
7
; and (f). Form drain
2
and source
3
.
Although Yamamoto et. al proposed the method of forming flash ROM embedded read only memory, the cost of a flash ROM with a stacking gate according to the prior art is still too high, and the process is very complex. Therefore a nitride read only memory with a similar function to flash ROM and having a lower cost instead of the conventional stacking gate flash ROM becomes a feasible idea. Read only memory is originally developed by Saifun Semiconductors Ltd. of Israel, with the structure and manufacturing method referred to in U.S. Pat. No. 5,966,603.
Strictly speaking, nitride read only memory is practically a kind of non-volatile memory, or more definitely, a kind of electrically erasable and programmable read only memory(EEPROM). The primary feature of the nitride read only memory structure is it utilizes an insulation dielectric layer composed of silicon nitride as a charge trapping medium. Since the silicon nitride layer is highly densified, the hot electrons tunneling through oxide layer will enter the silicon nitride layer and become trapped inside it. Flash ROM on the other hand, utilizes a polysilicon floating gate to store charges.
However, up to now there has been no disclosed prior art or essay which mentions a method of forming the mixed-signal circuit embedded with nitride read only memory and mask read only memory.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method of forming a system on chip(SOC), the system on chip embedded with a nitride read only memory area, a mask read only memory area, a periphery area and a mixed-signal area and its manufacturing method.
It is therefore another objective of the present invention to provide a method of forming a mixed-signal circuit system on chip embedded with nitride read only memory and mask read only memory, the method comprising manufacturing analog devices, such as a capacitor with ONO/NO to function as an inter-poly insulating layer and resistor device.
In the first preferred embodiment of the present invention, the method comprises: (1). Providing a semiconductor substrate, the surface of the semiconductor substrate divided into a memory area, a low voltage device area, a high voltage device area and a mixed-signal area; (2). Performing a shallow trench isolation process in order to form a plurality of shallow trench isolation areas on the surface of the semiconductor substrate for isolating devices; (3). Forming a bottom electrode of the capacitor atop the shallow trench isolation area in the mixed-signal circuit area; (4).Creating an ONO layer on the surface of the semiconductor substrate that covers the bottom electrode of the capacitor; (5). Forming a plurality of buried bit lines in the semiconductor substrate in the memory area; (6). Simultaneously forming an oxide layer atop each buried bit line and a gate oxide layer on the surface of the semiconductor substrate in the low voltage device area; (7). Depositing a polysilicon(PL
1
) layer on the semiconductor substrate; (8). Performing a photolithography and etching process in order to simultaneously form a plurality of bit lines in the memory area, a gate for low voltage MOS transistor in the low voltage device area; a gate for high voltage MOS transistor in the high voltage device area, a top electrode of the capacitor and a resistor in the mixed-signal circuit area; and (9). Performing a ROM code implantation process to a portion of the memory cells in the memory area in order to form a read only memory area.
It is an advantage of the present invention to utilize a nitride read only memory instead of the conventional stacking gate flash ROM. Therefore not only the cost can be reduced but also the manufacturing process can be simplified.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
patent: 5780341 (1998-07-01), Ogura
patent: 6177703 (2001-01-01), Cunningham

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