Symmetric device with contacts self aligned to gate

Details Symmetric device with contacts self aligned to gate Symmetric device with contacts self aligned to gate

2000-02-08

2002-09-03

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S252000, C257S332000, C257S346000, C257S382000, C257S384000, C257S393000, C257S412000

Reexamination Certificate

active

06445050

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method of forming a conductive stud self-aligned to a gate structure of a semiconductor device (e.g., a field effect transistor), wherein the conductive stud is conductively coupled to a drain region, or a source region, of the semiconductor device.
2. Related Art
Operation of a semiconductor device (e.g., a field effect transistor) that has a gate structure over a channel that is disposed between a drain and a source, requires conductive contacts (e.g., conductive studs) which conductively contact the drain and the source, such that the conductive contacts are insulatively separated from each other. In order to improve performance of the semiconductor device, gate structures are becoming smaller in size and this trend is expected to continue. As gate structure size diminishes, however, reliably aligning the conductive contacts with respect to the gate structure becomes increasingly difficult due to limited availability of space into which the conductive contacts may be positioned. As a result, conductive contacts may be placed in such close proximity of each other that undesired electrical shorting may occur.
A method is needed for positioning conductive contacts with respect to a gate structure, such that there is little risk of electrical shorting between the conductive contacts.
SUMMARY OF THE INVENTION
The present invention provides a first method of fabricating semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a gate structure, including:
forming a gate dielectric on a surface of the semiconductor substrate; and
forming a conductive gate aligned on the gate dielectric;
forming a drain region within the semiconductor substrate;
forming a source region within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate dielectric is over the channel region;
forming a first insulative spacer on a first sidewall of the gate structure;
forming a second insulative spacer on a second sidewall of the gate structure;
forming a first conductive stud in contact with the first insulative spacer, and in electrical contact with the drain region, wherein the first conductive stud includes a first conductive material; and
forming a second conductive stud in contact with the second insulative spacer, and in electrical contact with the source region, wherein the second conductive stud includes a second conductive material, and wherein a surface of the first conductive stud, a surface of the second conductive stud, and a surface of the gate structure are coplanar.
The present invention provides a first semiconductor device, comprising:
a semiconductor substrate having a drain region, a source region, and a channel region disposed between the drain region and the source region;
a gate structure on the semiconductor substrate, said gate structure including:
a gate dielectric on a portion of the channel region; and
a conductive gate aligned on the gate dielectric;
a first insulative spacer on a first sidewall of the gate structure;
a second insulative spacer on a second sidewall of the gate structure;
a first conductive stud in contact with the first insulative spacer, and in electrical contact with the drain region, wherein the first conductive stud includes a first conductive material; and
a second conductive stud in contact with the second insulative spacer, and in electrical contact with the source region, wherein the second conductive stud includes a second conductive material, and wherein a surface of the first conductive stud, a surface of the second conductive stud, and a surface of the gate structure are coplanar.
The present invention provides a method of fabricating semiconductor device, comprising the steps of:
providing a semiconductor substrate;
forming a gate structure, including:
forming a gate dielectric on a surface of the semiconductor substrate; and
forming a conductive gate aligned on the gate dielectric;
forming a drain region within the semiconductor substrate;
forming a source region within the semiconductor substrate, wherein a channel region is disposed between the drain region and the source region, and wherein the gate dielectric is over the channel region;
forming an insulative spacer on a sidewall of the gate structure; and
forming a conductive stud in contact with the insulative spacer, and in electrical contact with a diffusion region selected from the group consisting of the drain region and the source region, wherein the conductive stud includes a conductive material.
The present invention provides a semiconductor device, comprising:
a semiconductor substrate having a drain region, a source region, and a channel region disposed between the drain region and the source region;
a gate structure on the semiconductor substrate, said gate structure including:
a gate dielectric on a portion of the channel region; and
a conductive gate aligned on the gate dielectric;
an insulative spacer on a sidewall of the gate structure;
a conductive stud in contact with the insulative spacer, and in electrical contact with a diffusion region selected from the group consisting of the drain region and the source region, wherein the conductive stud includes a conductive material.
The present invention has the advantage of positioning conductive contacts with respect to a gate structure, such that there is little risk of electrical shorting between the conductive contacts.
The present invention has the advantage of offering substantial flexibility in spatially distributing conductive contacts, and also in spatially distributing conductive posts on the conductive contacts, so as to permit formation of a large variety of conductive pathways to the drain and the source.


REFERENCES:
patent: 4272881 (1981-06-01), Angle
patent: 4517729 (1985-05-01), Batra
patent: 5043790 (1991-08-01), Butler
patent: 5286667 (1994-02-01), Lin et al.
patent: 5393704 (1995-02-01), Huang et al.
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5804846 (1998-09-01), Fuller
patent: 5849622 (1998-12-01), Hause et al.
patent: 5885895 (1999-03-01), Liu et al.
patent: 5905293 (1999-05-01), Jeng et al.
patent: 5920098 (1999-07-01), Liaw
patent: 5920780 (1999-07-01), Wu
patent: 5926702 (1999-07-01), Kwon et al.

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