Methods of making interconnections for semiconductor circuits

Details Methods of making interconnections for semiconductor circuits Methods of making interconnections for semiconductor circuits

2000-01-07

2002-07-02

Lee, Eddie (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S672000

Reexamination Certificate

active

06413855

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates in general to interconnections within semiconductor circuits and methods of making the interconnections. More particularly, the present invention relates to interconnections which carry the greatest currents within the semiconductor circuits, referred to herein interchangeably as interconnects or large interconnects, and methods of making the interconnects to have low resistance and occupy reduced surface area. Since the large interconnects of the present application carry the greatest currents within the semiconductor circuits, they include, for example, power buses for conducting power within the semiconductor circuits.
A semiconductor circuit includes an array of devices which are interconnected by patterns of wiring lines formed of conductive material, some of the wiring lines connecting power to the devices. As the devices are scaled to smaller and smaller dimensions, formation of reliable interconnects becomes more and more difficult since the wiring lines need to be formed to occupy less chip space or surface area which is typically, at least in part, accomplished by reducing the width of the wiring lines. As the wiring lines are reduced in width, they eventually become so narrow that to reduce them further results in resistance levels which are too great for reliable operation of the semiconductor circuits. Resistance levels due to narrow wiring line widths is particularly problematic for power buses and other large interconnects which carry the highest currents within the semiconductor circuit.
To overcome the problems of further reduction of width for wiring lines, the depth of the lines has been increased. A method for increasing the depth of wiring lines is known as a damascene process which is named after the inlaid metal technique used in ancient Damascus to decorate swords and the like. In the damascene process, channels are etched into a generally planar insulation layer and a layer of conductive material is then formed over the insulation layer to fill the channels and form conductive ribs which are coupled to contact locations beneath the insulation layer. A planarization operation is then performed, for example by chemical mechanical planarization (CMP), to separate the inlaid ribs from one another.
Unfortunately, wiring lines used for large interconnects of a semiconductor circuit which are formed as ribs and produced, for example, by the damascene process, have height limitations such that the conductivity of the corresponding large interconnects is limited. Accordingly, this solution to the problem of providing ever smaller area wiring lines for interconnections is limited as well.
There is, thus, a need for improved interconnections for semiconductor circuits which will allow wiring lines to be formed within smaller surface areas yet provide lower resistances than can be produced by wiring lines formed as isolated conductive ribs.
SUMMARY OF THE INVENTION
This need is met by the methods and apparatus of the invention of the present application wherein interconnects associated with a semiconductor structure are formed by an interconnect line having at least one and commonly two or more ribs extending generally orthogonally from the interconnect line. In the illustrated embodiments of the interconnects, the interconnect line is generally horizontal and the associated rib or ribs extend generally vertically from the interconnect line. The resulting interconnect occupies a surface area corresponding to the surface area of the interconnect line yet includes the conductive material of the interconnect line and the rib or ribs which extend therefrom so that it has substantially less resistance than the interconnect line alone or the rib or ribs alone. The rib or ribs and interconnect line are produced from a conductive layer, with or without a barrier layer, formed over an insulation layer after the insulation layer has been appropriately masked and etched.
The ribs can be formed over conductive plugs which are preformed through an insulation layer formed over the semiconductor structure with the conductive plugs being aligned with contact locations on the semiconductor structure. The ribs and conductive plugs can also be formed together by forming a mask within an insulation layer or between two insulation layers to locate the conductive plugs. The upper insulation is masked and etched to form trenches with openings through the bottom insulation being etched through openings in the mask with the remainder of the mask preventing the bottom insulation from being etched other than to form openings for the conductive plugs. A layer of conductive material, with or without a barrier layer, is formed to fill the conducive plug openings, corresponding openings in the mask and the trenches.
It is, thus, an object of the present invention to produce semiconductor circuit interconnections which have low resistance relative to the surface area occupied by the interconnections; and, to produce semiconductor circuit interconnections having an interconnection line with at least one rib extending generally orthogonally from the interconnection line.
Other objects and advantages of the invention will be apparent from the following description, the accompanying drawings and the appended claims.


REFERENCES:
patent: 4789648 (1988-12-01), Chow et al.
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 5162250 (1992-11-01), Clark
patent: 5399235 (1995-03-01), Mutsaers et al.
patent: 5466639 (1995-11-01), Ireland
patent: 5767546 (1998-06-01), Williams et al.
patent: 5792691 (1998-08-01), Koga
patent: 5895261 (1999-04-01), Schinella et al.
patent: 5932928 (1999-08-01), Clampitt
patent: 5977599 (1999-11-01), Adrian
patent: 6184075 (2001-02-01), Kim
patent: 6187660 (2001-02-01), Gardner
patent: 6187689 (2001-02-01), Tabara
patent: 6242811 (2001-06-01), Chen et al.

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