Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-10-30
2002-07-23
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06425101
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to integrated circuits. More specifically, the present invention relates to a method and a system for testing and debugging integrated circuits.
BACKGROUND OF THE INVENTION
It should be noted that throughout this document, test protocols will be construed to generally include debug protocols.
Circuits are commonly constructed on printed circuit boards (PC boards). These circuits are often complex and can include a large number of integrated circuits (ICs), where the ICs can be incorporated into a wide variety of packages. The number of ICs and the variety of packages on a PC board makes the functionality of the ICs and the interconnect between them difficult to test.
In order to test complex PC board circuits, test architectures and test buses such as boundary scan tests have been developed and are well known in the art. An IEEE standard for this type of test (defined by generic signals TCK, TMS, TDI, TDO, TRST) architecture has been developed and is known as IEEE 1149.1 or JTAG. However, for a boundary scan test to effectively verify a PC board circuit under IEEE 1149.1 standard, each of the ICs on the PC board to be tested must include an associated test architecture (referred to as boundary scan) that is also JTAG compliant.
FIG. 1
illustrates a conventional JTAG compliant test architecture
100
. The test architecture
100
includes a master controller
102
connected to a slave JTAG target
104
by way of JTAG compliant connectors
106
and
108
. The JTAG target
104
includes a serial register chain
110
formed of serially interconnected integrated circuits IC
112
through IC
118
. During a boundary scan test, the master controller
102
serially scans and tests a predetermined series of databits that contains both the control and data information into the serial register chain
110
. Typically, this control and data information is provided by a particular test protocol executed by the master controller
102
specific for the boundary scan test being performed. The control information controls a state machine included in on each of IC
112
through
118
. The state machine in turn uses registers and the supplied data information to test the board interconnects (
120
through
124
) and the associated ICs. One of the registers on each IC is a boundary scan register that includes all the input, output, and input/output ports on the IC.
In some situations, it may not be desirable to test one or more of the integrated circuits included in the slave device
102
. In such a case, a software “bypass” is performed by using the JTAG instruction “BYPASS” prior to the start of the boundary scan test to bypass these integrated circuits. In order to bypass a particular integrated circuit(s), a “BYPASS” JTAG instruction specific to the integrated circuit(s) to be bypassed is generated. The state machine included in the integrated circuit responds to the bypass instruction by causing any received data and control information to bypass the internal circuitry of the integrated circuit. This, in effect, removes the particular IC from the boundary scan test being performed.
However, in some cases, defects within an integrated circuit prevent a software bypass from being performed. In such a case, it would be impossible to perform an accurate boundary scan test within the test architecture
100
since it would be impossible to bypass the defective integrated circuit. Therefore, in order to properly test the remaining integrated circuits, physical replacement of the defective integrated circuit would be required. In complex circuit boards, the removal and replacement of a particular integrated circuit may be too costly in time or expense to be practical.
By embedding debug circuitry within integrated circuits, designers have been able to greatly enhance the capability to economically debug integrated circuits reducing the costs of design and implementation. This is especially desirable for complex and expensive integrated circuits such as microprocessors and the like. Therefore, integrated circuit manufacturers are highly motivated to include such on chip debug capabilities in their most complex and costly integrated circuits. However, the test architecture
100
is incapable of supporting embedded and proprietary debug protocols developed by, for example, Siemens Microelectronics, Inc. of San Jose, Calif., since the JTAG connectors
106
and
108
cannot be used to carry the required debug information to the JTAG target
104
.
In view of the foregoing, it is desirable to provide an improved and programmable JTAG network architecture which supports embedded debug protocols.
SUMMARY OF THE INVENTION
An apparatus for testing a plurality of integrated circuits where each of the integrated circuits has an associated test protocol and at least one of the integrated circuits has an associated on-chip debug protocol is disclosed. More specifically, the apparatus includes a master controller operable to perform the test protocol associated with each of the integrated circuits including the on-chip debug protocol. The apparatus also includes a programmable switch for selectively forming test loops between the master controller and selected ones of the integrated circuits as directed by the master controller according to configuration data. The test loops facilitate execution of selected ones of the test protocols. The apparatus includes a data bus for connecting the master controller to each of the integrated circuits. The data bus is configured to transmit data and control signals between the master controller and the integrated circuits, as well as for facilitating execution of the on-chip debug protocol.
In one preferred embodiment, the master controller includes a JTAG controller connected to the data bus that is configured to execute a JTAG test protocol as well as an On-Chip-Debug-Support (OCDS) controller connected to the data bus that is configured to execute the OCDS test protocol. The master controller also includes a programmable switch controller connected to the programmable switch configured to provide a switch control signal to the programmable switch controller which responds by connecting the JTAG controller, as needed, to the integrated circuit being tested.
A test system for testing JTAG compliant integrated circuits and JTAG compliant integrated circuits having on-chip debug support (OCDS) integrated circuits is also disclosed. In a preferred embodiment, a host computer connected to the master controller provides selected test protocols, as needed, to the master controller.
Another aspect of the invention includes a printed circuit board. The printed circuit board includes a plurality of integrated circuits. Each of the integrated circuits has an associated test protocol and at least one of the integrated circuits includes an embedded debug circuit. The embedded debug circuit, in turn, has an associated on-chip debug protocol. The printed circuit board also includes a plurality of conductors for forming test loops between each of the integrated circuits and external test circuitry. The test loops facilitate execution of selected ones of the test protocols. The printed circuit board also includes a data bus connected to each of the integrated circuits. The data bus is configured to transmit data and control signals between the integrated circuits and the external test circuitry. The data bus also facilitates execution of the on-chip debug protocol.
A method for testing a plurality of integrated circuits using a master controller and a programmable switch to selectively connect the master controller with selected ones of the integrated circuit is also disclosed. Each integrated circuit has an associated test protocol and at least one of the integrated circuits includes an embedded debug circuit having an associated on-chip debug protocol. The method includes the following operations: providing the test protocols to the master controller; selecting a first test protocol; transmitting first switch configuration data associate
Chung Phung M.
Fish & Richardson P.C.
Infineon Technologies North America Corp.
Torres Joseph D.
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