Method of fabricating semiconductor device including...

Details Method of fabricating semiconductor device including... Method of fabricating semiconductor device including...

2001-09-18

2002-07-02

Christianson, Keith (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S267000, C438S286000

Reexamination Certificate

active

06413821

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method of fabricating a semiconductor device including a memory region in which nonvolatile semiconductor memory devices including two charge storage regions for one word gate are arranged in an array and a logic circuit region.
BACKGROUND
As one type of nonvolatile semiconductor memory device, a Metal Oxide Nitride Oxide Semiconductor (MONOS) or Silicon Oxide Nitride Oxide Silicon (SONOS) memory device is known. In such a memory device, a gate insulating layer between a channel region and a control gate is formed of a laminate consisting of a silicon oxide layer and a silicon nitride layer, and a charge is trapped in the silicon nitride layer.
A device shown in
FIG. 22
is known as such a MONOS nonvolatile semiconductor memory device (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS memory cell
100
, a word gate
14
is formed on a semiconductor substrate
10
with a first gate insulating layer
12
interposed. A first control gate
20
and a second control gate
30
are disposed on either side of the word gate
14
in the shape of sidewalls. A second gate insulating layer
22
is present between the bottom of the first control gate
20
and the semiconductor substrate
10
. An insulating layer
24
is present between the side of the first control gate
20
and the word gate
14
. A second gate insulating layer
32
is present between the bottom of the second control gate
30
and the semiconductor substrate
10
. An insulating layer
34
is present between the side of the second control gate
30
and the word gate
14
. Impurity layers
16
and
18
which form either a source region or a drain region are formed in the semiconductor substrate
10
between the control gate
20
and the control gate
30
facing each other in the adjacent memory cells.
As described above, one memory cell
100
includes two MONOS memory elements, one on each side of the word gate
14
. These two MONOS memory elements are controlled separately. Therefore, one memory cell
100
is capable of storing 2 bits of information.
SUMMARY
An objective of the present invention is to provide a method of fabricating a semiconductor device including MONOS nonvolatile semiconductor memory devices having two charge storage regions, in which a memory region including MONOS memory cells and a logic circuit region including a peripheral circuit for a memory and the like are formed on the same substrate.
The present invention provides a method of fabricating a semiconductor device including a memory region including nonvolatile memory devices and a logic circuit region including a peripheral circuit for the nonvolatile memory devices, the method comprising the following steps in that order:
a step of forming a first insulating layer over a semiconductor layer,
step of forming a first conductive layer over the first insulating layer,
a step of forming a stopper layer over the first conductive layer,
a step of removing the stopper layer in the logic circuit region,
a step of patterning the first conductive layer in the logic circuit region, thereby forming gate electrodes of insulated gate field effect transistors in the logic circuit region,
a step of forming sidewall insulating layers at least on both sides of the gate electrodes,
a step of forming a protective insulating layer in the logic circuit region so as to cover at least the gate electrodes,
a step of patterning the stopper layer and the first conductive layer in the memory region,
a step of forming an ONO film over the entire surface of the memory region and the logic circuit region,
a step of forming a second conductive layer over the ONO film,
a step of anisotropically etching the second conductive layer, thereby forming control gates in the shape of sidewalls at least on both sides of the first conductive layer in the memory region with the ONO film interposed,
a step of removing the protective insulating layer in the logic circuit region,
a step of forming first impurity layers which form either a source region or a drain region of the nonvolatile memory devices and second impurity layers which form either a source region or a drain region of the insulated gate field effect transistors,
a step of forming silicide layers on the surfaces of the first impurity layers, the second impurity layers and the gate electrodes,
a step of forming a second insulating layer over the entire surface of the memory region and the logic circuit region,
a step of polishing the second insulating layer so that the stopper layer is exposed in the memory region and the gate electrodes are not exposed in the logic circuit region,
a step of removing the stopper layer in the memory region, and
a step of patterning the first conductive layer in the memory region, thereby forming word gates of the nonvolatile memory devices in the memory region.


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09/953,855 Sep. 18, 2001.
Hayashi, Yutaka et al., “Twin MONOS Cell with Dual Control Gates”,2000 IEEE Symposium on VLSI Technology Digest of Technical Papers.
Chang, Kuo-Tung et al., “A New SONOS Memory Using Source-Side Injection for Programming”,1998 IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen, Wei-Ming et al., “A Novel Flash Memory Device with SPlit Gate Source Side Injection and ONO Charge Storage Stack (SPIN)”,1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.

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