Method to form MOS transistors with shallow junctions using...

Details Method to form MOS transistors with shallow junctions using... Method to form MOS transistors with shallow junctions using...

2000-07-12

2002-01-01

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S528000, C438S308000

Reexamination Certificate

active

06335253

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming MOS transistors with shallow junctions using laser annealing in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Sub-0.1 micron MOS technology requires the use of abrupt, ultra-shallow junctions for deep source and drains and for source and drain extensions. Traditional processing approaches have used ion implantation followed by rapid thermal annealing (RTA) to activate the implanted ions. RTA is used rather than a traditional thermal process to limit the thermal budget of the annealing process. However, RTA may not be capable for sub-0.1 micron technology because the RTA thermal ramp-up and ramp-down times are too large and can cause too much diffusion in the substrate. In addition, two RTA cycles are required: one to form the source and drain extension and one to form the deep source and drain.
RTA is also used in the art in the formation of silicide, particularly self-aligned silicide (salicide). A metal layer is first deposited overlying the integrated circuit. A RTA is performed to promote the reaction between the metal layer and silicon for the formation of silicide where the polysilicon gate and the source and drain junctions contact the metal layer. Once again, RTA may not be a capable process for sub-0.1 micron formation of silicide because of the large thermal budget. In addition, it is not possible to combine the RTA used for silicide formation with that used for source and drain junction activation.
Several prior art approaches disclose methods to form self-aligned silicide or to form source and drain junctions in the manufacture of integrated circuit devices. U.S. Pat. No. 5,953,615 to Yu teaches a method to form deep source and drain junctions and shallow source and drain extensions in a single process. Spacers are formed. An ion beam is used to amorphize the silicon to two different depths. Spacers are removed and not reformed. A single dopant implantation is performed. U.S. Pat. No. 5,888,888 to Talwar et al discloses a method to form silicide. Amorphous regions are formed in the polysilicon gate and in the substrate. A metal layer is then deposited. Laser light is used to form silicide. The metal layer is explicitly not melted by the laser light. A thermal anneal is then performed to crystallize the silicide. No capping layer is used during silicidation. U.S. Pat. No. 5,998,272 to Ishida et al teaches a method to form a MOSFET with deep source and drain junctions and shallow source and drain extensions. Sidewall spacers are removed after formation of source and drain junctions and salicide. A laser doping process is used in one embodiment. U.S. Pat. No. 5,937,325 to Ishida discloses a method to form silicide on an MOS gate. A titanium layer is deposited. A laser anneal is performed to form silicide. After removing unreacted metal, an RTA is performed to decrease the resistivity of the silicide. U.S. Pat. No. 5,908,307 to Talwar et al teaches a method to form MOS transistors with ultra-shallow junctions. After a pre-amorphizing ion implantation, a projection gas immersion laser doping (P-GILD) process is used to deposit the junctions. U.S. Pat. No. 5,956,603 to Talwar et al discloses a method to form shallow junction MOS transistors. Amorphous regions are ion implanted and then laser annealed. The deep source and drain junctions are annealed separately from the shallow extension junctions. The deep junctions and the shallow extension junctions are formed in separate process step. U.S. Pat. No. 5,966,605 to Ishida teaches a method to form a transistor. An ion implant is performed to dope the gate and the source and drain regions. A laser anneal is performed on the polysilicon gate but the unactivated ions do not diffuse in the source and drain regions. An RTA is then performed to activate the source and drain ions.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method to form MOS transistors in the manufacture of an integrated circuit device.
A further object of the present invention is to form shallow source and drain extensions using a laser anneal.
Another further object of the present invention is to form deep source and drain junctions using a laser anneal.
A still further object of the present invention is to simultaneously form shallow source and drain extensions and deep source and drain junctions using a single laser anneal.
Another further object of the present invention is to form self-aligned silicide on the gate, drain, and source of an MOS transistor using a laser anneal.
A still further object of the present invention is to simultaneously form shallow source and drain extensions and self-aligned silicide on the gate, drain, and source of an MOS transistor using a single laser anneal.
In accordance with the objects of this invention, a new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Each gate comprises a gate oxide layer overlying the semiconductor substrate and a polysilicon layer overlying the gate oxide layer. Temporary sidewall spacers are formed on the gates. The temporary sidewall spacers are over etched to achieve a selected sidewall width. Ions are implanted into the exposed semiconductor substrate to form an amorphous layer. A deeper amorphous layer forms adjacent to the spacers while a shallower amorphous layer forms under the spacers. The temporary sidewall spacers are removed. Ions are implanted into the exposed semiconductor substrate to form lightly doped junctions in the shallower amorphous layer. Permanent sidewall spacers are formed on the gates. Ions are implanted into the semiconductor substrate to form heavily doped junctions in the deeper amorphous layer. A capping layer is deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the heavily doped junctions diffuse in the deeper amorphous layer and in the lightly doped junctions diffuse in the shallower amorphous layer. The deep source and drain junctions and the shallow source and drain extensions for the transistors are thereby simultaneously formed. The capping layer is removed to complete the MOS transistors in the manufacture of the integrated circuit device.
Also in accordance with the objects of this invention, a new method of forming MOS transistors with shallow source and drain extensions and deep source and drain junctions in the manufacture of an integrated circuit device has been achieved. Gates are provided overlying a semiconductor substrate. Each gate comprises a gate oxide layer overlying the semiconductor substrate and a polysilicon layer overlying the gate oxide layer. Ions are implanted into the exposed semiconductor substrate to form shallower amorphous layer. Ions are implanted into the exposed semiconductor substrate to form lightly doped junctions in the shallower amorphous layer. Sidewall spacers are formed on the gates. Ions are implanted into the exposed semiconductor substrate to form a deeper amorphous layer. Ions are implanted into the semiconductor substrate to form heavily doped junctions in the deeper amorphous layer. A capping layer is deposited overlying the semiconductor substrate and the gates to protect the semiconductor substrate during irradiation. The semiconductor substrate is irradiated with laser light to melt the amorphous layer while the crystalline regions of the semiconductor substrate remain in solid state. Ions in the heavily doped junctions diffuse in the deeper amorphous layer and in the lightly doped junctions diffuse in

Affiliated with

Also associated with

Rating

Method to form MOS transistors with shallow junctions using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to form MOS transistors with shallow junctions using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to form MOS transistors with shallow junctions using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2873772