Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-10
2002-05-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S385000, C438S532000
Reexamination Certificate
active
06387745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more specifically, it relates to a semiconductor device having a polydiode element which is improved to be resistant to surge or contamination.
2. Description of the Prior Art
A nonvolatile semiconductor device, which requires a high voltage (10 to 20 V in general) for a write/erase operation for a memory cell, has generally required two external power sources (Vpp/Vcc, Vpp: a high voltage of about 12 V). In recent years, however, a single power source Vcc is employed for attaining commonness with other devices. In this case, the nonvolatile semiconductor device is provided in its chip with a built-in circuit for stepping up the power supply voltage Vcc to the high voltage Vpp.
A charge-pump step-up circuit, which is generally employed in an LSI, has various problems. A textbook “Design of CMOS VLSI” (Baifu-Kan, pp. 192 to 193) describes an exemplary charge-pump step-up circuit, its principle and its problems. According to this literature, the charge-pump step-up circuit serially connects a MOS diode with a unit of a capacitance and performs a step-up operation with two clocks of different timing. However, a rectifying device is formed by the MOS diode. The threshold voltage vth of the MOS diode gradually increases as the number of stages increases due to a substrate bias effect, and hence step-up efficiency is disadvantageously deteriorated with the number of stages.
IEEE International Solid-State Circuits Conference (1995) TA7.2 discloses a charge-pump step-up circuit forming a P-N junction diode on a substrate not by a MOS diode but through a triple well structure of the substrate. In this case, the efficiency is not deteriorated by the substrate bias effect. However, the process is complicated to increase the cost due to formation of the triple well structure. Further, the capacitance between an N well and the substrate serves as a parasitic capacitance due to formation on the substrate, to disadvantageously deteriorate the efficiency.
FIG. 38
shows an EEPROM comprising a charge-pump step-up circuit utilizing a P-N junction diode (hereinafter referred to as a polydiode element)
2
employing polysilicon, which is disclosed in “Lateral Polysilicon p-n Diodes (J. Electrochem. Soc., Vol. 125, October 1978, p. 1648). This EEPROM also appears in IEEE J. Solid-State Circuits, Vol. SC-16, June 1981, p. 195 and IEEE Trans. Electron Devices, Vol. ED-27, July 1980, p. 1211.
Referring to
FIG. 38
, the polydiode element
2
is formed on an SiO
2
film
1
. An interlayer isolation film
3
is formed on the SiO
2
film
1
, to cover the polydiode element
2
. Aluminum wires
4
are connected to a P-type layer and an N-type layer of the polydiode element
2
through contact holes provided in the interlayer isolation film
3
.
In case of employing the polydiode element
2
shown in
FIG. 38
, no problem of a substrate bias effect or a parasitic capacitance is caused dissimilarly to the case of employing a MOS diode or a P-N diode formed on a substrate. However, the aluminum wires
4
are directly electrically in contact with the polydiode element
2
to cause reaction on the interfaces therebetween, to disadvantageously result in dispersion of contact resistance as well as dispersion of the characteristics of the polydiode element
2
. Further, such a conventional polydiode element
2
is not resistant to electrical noise such as surge. Further, the conventional polydiode element
2
shown in
FIG. 38
is not resistant to contamination.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, an object of the present invention is to provide a semiconductor device having a high-performance polydiode element (P-N junction element).
Another object of the present invention is to provide a charge-pump step-up circuit of high performance with such a polydiode element.
Still another object of the present invention is to provide a high-performance nonvolatile semiconductor memory device with such a step-up circuit.
A further object of the present invention is to provide a method of fabricating a semiconductor device having such a polydiode element with neither additional step nor excess cost.
A semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a major surface. An element isolation oxide film is provided on the major surface of the semiconductor substrate. A polydiode element having a P-type layer and an N-type layer is provided on the element isolation oxide film. An interlayer isolation film is provided on the major surface of the semiconductor substrate, to cover the polydiode element. A first contact hole exposing the P-type layer and a second contact hole exposing the N-type layer are provided in the interlayer isolation film. A first resistive element connected with the P-type layer is provided in the first contact hole. A second resistive element connected with the N-type layer is provided in the second contact hole. A first wiring layer is connected to the P-type layer through the first resistive element. A second wiring layer is connected to the N-type layer through the second resistive element.
According to this aspect of the present invention, the first wiring layer is connected to the P-type layer through the first resistive element and the second wiring layer is connected to the N-type layer through the second resistive element, whereby the semiconductor device is resistant to electrical noise such as surge.
According to a second aspect of the present invention, the semiconductor device further includes a nonvolatile semiconductor storage element, which is formed on the semiconductor substrate, having a floating gate of polysilicon, and the polydiode element is made of the same material as the floating gate.
According to this aspect of the present invention, the polydiode element, which is made of the same material as the floating gate, can be formed simultaneously with the floating gate, whereby the semiconductor device can be fabricated with no additional step.
According to a third aspect of the present invention, the first and second resistive elements of the semiconductor device are formed by barrier metals and/or tungsten plugs. Thus, the first and second resistive elements can be made of general materials.
According to a fourth aspect of the present invention, the N-type layer of the semiconductor device consists of an N
+
-type layer which is connected with the P-type layer and an N
++
-type layer which is connected with this N
+
-type layer.
According to this aspect of the present invention, the forward characteristic of the polydiode element is improved.
According to a fifth aspect of the present invention, the polydiode element of the semiconductor device is built in a charge-pump step-up circuit as a part thereof.
According to this aspect of the present invention, the polydiode element having the aforementioned characteristics is built in the charge-pump step-up circuit as a part thereof, whereby the charge-pump step-up circuit is resistant to electrical noise such as surge.
A semiconductor device according to a sixth aspect of the present invention relates to a nonvolatile semiconductor memory device. The semiconductor device comprises a semiconductor substrate. A nonvolatile semiconductor storage element having a floating gate, a control gate and an interpoly dielectric film provided between the floating gate and the control gate is formed on the semiconductor substrate. An element isolation oxide film is formed on a surface of the semiconductor substrate. A polydiode element having a P-type layer and an N-type layer of the same material as the floating gate is provided on the element isolation oxide film. An interlayer isolation film is provided on the semiconductor substrate, to cover the polydiode element. A first contact hole exposing the P-type layer and a second contact hole exposing the N-type layer are provided in the interlayer isolation
Mihara Masaaki
Onoda Hiroshi
Takada Hiroshi
Chaudhari Chandra
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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