Stacked capacitor construction

Details Stacked capacitor construction Stacked capacitor construction

1996-04-05

2002-01-15

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S303000

Reissue Patent

active

RE037505

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to three dimensional sack capacitors and the fabrication thereof.
BACKGROUND OF THE INVENTION
As DRAMs increase in memory cell density, there is a continuous challenge to maintain sufficiently high storage capacitance despite decreasing cell area A principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors. This invention concerns stacked capacitor cell constructions.
With the conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance. However, some attempts have been made to provide constructions to increase capacitance, whereby the back side of one capacitor terminal is used to store charge. Such is shown by way of example by T. Ema et al. “3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMS”, IEDM Tech. Digest, pp. 592, 595, 1988 and S. Inoue et al., “A Spread Stacked Capacitor (SSC) Cell For 64 MBit DRAMs”, IEDM Tech. Digest, pp. 31-34, 1989.
One standard prior art technique for forming a stacked “crown” cell capacitor is described with reference to
FIGS. 1-4
. “Crown” capacitors are characterized by upward spire-like, or fin-like projections, thereby increasing surface area and corresponding capacitance as compared to planar capacitors.
FIG. 1
illustrates a semiconductor wafer fragment
10
comprised of a bulk substrate
12
, word lines
14
,
16
, field oxide region
18
, and an active area
20
for connection with a capacitor. Wafer
10
also comprises a layer of insulating dielectric
22
through which a desired contact opening
24
has been provided to active area
20
. Referring to
FIGS. 1 and 2
, contact opening
24
has an elliptical or circular shape with walls
26
. The vertical lines illustrated in
FIG. 1
illustrate shading only for identifying sidewalls
26
and depicting a smooth surface which arcs into the page. Such lines do not indicate texture or other patterning. Sidewalls
26
are typically smooth and straight. The elliptical shape of contact
24
can be produced by depositing a photoresist film over the bulk substrate
10
and transferring the contact
24
pattern by photolithographic means using the proper image mask.
Referring to
FIG. 3
, a layer
28
of conductive material, such as conductively doped polysilicon, is deposited atop wafer
10
and to within contact opening
24
. Layer
28
will provide the storage node poly for formation of one of the capacitor plates.
Referring to
FIG. 4
, polysilicon layer
28
is first chemical mechanical polished or resist planerization dry etched to be flush with the upper surface of insulating layer
22
. Thereafter, insulating layer
22
is etched selectively relative to polysilicon to produce an isolated storage node
30
having the illustrated crown portions projecting upwardly from layer
22
. Thereafter, a cell dielectric would be deposited, followed by a cell polysilicon layer to complete the capacitor construction.
It is an object of this invention to enable such and similar stacked capacitor constructions to have increased capacitance.


REFERENCES:
patent: 5049517 (1991-09-01), Liu et al.
patent: 5068199 (1991-11-01), Sandhu
patent: 5082797 (1992-01-01), Chan et al.
patent: 5110752 (1992-05-01), Lu
patent: 5138411 (1992-08-01), Sandhu
patent: 5227651 (1993-07-01), Kim et al.
patent: 5519238 (1996-05-01), Lu
patent: 5623243 (1997-04-01), Watanabe et al.
patent: 2-166760 (1990-06-01), None
patent: 2-203557 (1990-08-01), None
patent: 3-266460 (1991-11-01), None
Ema et al “3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs” IEDM Tech. Digest, 1988, pp. 592-595.*
S. Inoue et al “A Spread Stacked Capacitor (SSC) Cell for 64 MBit DRAMs” IEDM Tech. Digest, 1989, pp. 31-34.

Affiliated with

Also associated with

Rating

Stacked capacitor construction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked capacitor construction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked capacitor construction will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2871817