Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-05
2002-05-21
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257S328000
Reexamination Certificate
active
06391699
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to semiconductor technology, and in particular, to a method of manufacturing a trench doubly-diffused Metal Oxide Semiconductor Field Effect transistor (trench DMOS transistor) using selective growth epitaxy.
A cross-sectional view of a typical n-channel trench DMOS transistor
10
is shown in FIG.
1
. It includes an n-type substrate
100
upon which an n-type epitaxial layer
102
is typically grown. A p-type body layer
108
covers epitaxial layer
102
and one or more trenches
100
extend through the body layer
108
and a portion of the epitaxial layer
102
. Gate oxide layer
104
lines the sidewalls and bottom of each trench
100
and a conductive material
106
, typically doped polysilicon, lines gate oxide layer
104
and fills each trench
100
. N+ source regions
110
flank each trench
100
and extend a predetermined distance into body layer
108
. Heavy body regions
112
are positioned within body layer
108
and between source regions
110
and extend a predetermined distance into body layer
108
. Finally, dielectric caps
114
cover the filled trenches
100
and also partially cover the source regions
110
.
During fabrication of the trench DMOS transistor
10
, an anisotropic etch step is typically performed to form trenches
100
. An anisotropic etch is used, as opposed to an isotropic etch, since an anisotropic etch etches substantially in one direction, which in this example, is vertical and downward. A drawback of administering an anisotropic etch is that the sidewalls become damaged, i.e. silicon surface defects are created. This leads to a degraded gate oxide
104
to trench sidewall interface and a concomitant degradation in the quality of the gate oxide
104
itself.
After trenches
100
are formed, a dielectric layer such as silicon dioxide (or oxide) is typically grown over the bottom and sidewalls of the trench to form a gate oxide. Simultaneous formation of the oxide at the bottom and on the sidewalls of the trenches limits the thickness of the oxide that can be grown on the bottom of the trenches
100
, since growth on the sidewalls eventually pinches off growth on the bottom of the trenches
100
. A thin oxide on the bottom of the trench is undesirable since it leads to a lower breakdown voltage of the device and an undesirably large gate-to-drain capacitance.
Limiting oxide growth on the trench sidewalls while growing oxide on the bottom of the trench can be accomplished by using a masking technique such as LOCOS (Local Oxidation of Silicon). Unfortunately, this sidewall masking technique creates problems such as oxide stress near the corners of a trench and formation of a “bird's head” at the upper and lower comers of the trench. These bird's heads are undesirable. For example, the presence of bird's heads at the upper trench corners leads to step-coverage problems of overlying metal layers, due to the uneven surface topology caused by the bird's heads. While an etchback of the LOCOS layer can somewhat reduce the presence of the bird's head, there still remains the problem of reliably growing an oxide layer on the bottom of the trench to a predetermined thickness.
SUMMARY OF THE INVENTION
In a first aspect of the invention, a method of forming a trench in a semiconductor substrate is disclosed. The method comprises the steps of: providing a semiconductor substrate; forming a pillar of dielectric material on the substrate, the pillar having a top surface and a predetermined thickness; forming a semiconductor layer over the substrate and around and over the top surface of the pillar; forming a masking layer over the semiconductor layer, the masking layer having a trench opening access that exposes a portion of an upper surface of the semiconductor layer and being in substantial vertical alignment with the pillar; and forming a trench through the trench opening access by anisotropically etching the semiconductor layer down to the top surface of the pillar. Preferably, the dielectric pillar is silicon dioxide and is formed via thermal oxidation.
In a second aspect of the invention, a method of manufacturing a trench MOSFET is disclosed. The method comprises the steps of: providing a semiconductor substrate having a first conductivity type; forming a first semiconductor layer over the substrate, the first semiconductor layer having the first conductivity type; forming a plurality of dielectric pillars across a surface of the first semiconductor layer, each pillar having a top surface and predetermined height; forming a second semiconductor layer having the first conductivity type over the first semiconductor layer and around and over the top surfaces of the pillars; forming a third semiconductor layer over the second semiconductor layer, the third semiconductor layer having a second conductivity type; forming a masking layer over the third semiconductor layer, the masking layer defining a plurality of trench opening accesses that expose portions of an upper surface of the third semiconductor layer and being in substantial vertical alignment with the pillars; forming a plurality of trenches through the trench opening accesses by anisotropically etching the third semiconductor layer and a portion of the second semiconductor layer and down to the top surfaces of the pillars; removing the masking layer; lining sidewalls of the trenches with a dielectric material; and lining the dielectric material and filling the trenches with a conductive material.
In an alternative embodiment to the second aspect of the invention source and heavy body regions are formed by standard implant and drive techniques and a dielectric cap is then formed over openings to the trenches and over a portion of the source regions.
In a third aspect of the invention a trench structure is disclosed, the trench structure comprising: A trench structure, comprising: a semiconductor substrate; a first semiconductor layer formed over the substrate; a second semiconductor layer selectively formed over the first semiconductor layer; a trench extending from an exposed primary surface of the second semiconductor layer and through the first and second semiconductor layers; and a dielectric column positioned at the bottom of the trench, the column having a substantially flat upper surface and a precisely controlled and predetermined thickness. Preferably the dielectric column is formed by thermal oxidation.
In a fourth aspect of the invention a trench MOSFET is disclosed, the trench MOSFET, comprising: a substrate having a first conductivity type; a first semiconductor layer having the first conductivity type formed over the substrate; a second semiconductor layer having the first conductivity type selectively formed over the first semiconductor layer; a third semiconductor layer having a second conductivity type selectively formed over the second semiconductor layer; a plurality of trenches extending from an exposed primary surface of the third semiconductor layer and through the third and second semiconductor layers, each trench defined by a bottom and walls; a dielectric column positioned at the bottom of each trench, the column having a substantially flat upper surface and a precisely controlled and predetermined thickness; a dielectric material lining the walls of the trenches; and a conductive material lining the dielectric material and filling the trenches.
In a fifth aspect of the invention dielectric caps are formed over openings of the trenches in the trench MOSFET described in the previous paragraph. These caps isolate the source regions from the gate region of the trench MOSFET. Each cap has lateral dimensions that are substantially equal to the lateral dimensions of the trenches. These dimensions allow a lower trench-to-trench pitch than what can be realized in prior art trench MOSFETs.
A further understanding of the nature and advantages of the inventions herein may be realized by reference to the remaining portions of the specification and the attached drawings.
REFERENCES:
pate
Madson Gordon K.
Sharp Joelle
Fairchild Semiconductor Corporation
Hoang Quoc
Nelms David
Townsend and Townsend / and Crew LLP
Winters William E.
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