Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-28
2002-05-07
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000, C438S258000, C438S972000
Reexamination Certificate
active
06383870
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to the field of electronic devices and, more particularly, to improved architectures for semiconductor devices that include nitride layers that are transmissive to ultraviolet radiation.
BACKGROUND OF THE INVENTION
The formation of modern integrated circuit elements often includes chemical etch processes where various chemicals react with materials in an integrated architecture being constructed to remove portions of the materials. In these processes, certain materials are often used to protect portions of the device from chemicals being used to form other portions of the device. In these processes, developers utilize the selective nature of certain processes to erode one type of material and leave another type of material substantially unaffected. In this context, silicon nitride is often used as an etch stop for chemical etching processes used to etch silicon dioxide layers. By using silicon nitride layers as an etch stop, device architectures can be compactly spaced and overall device density can be increased.
A significant problem arises, however, when silicon nitride etch stop layers are used with flash memory or electrically erasable programmable read only memory (EEPROM) or UV EPROM devices. These devices typically utilize a floating gate that stores charge representative of data stored by the memory device. This charge is placed on the floating gate through operations that result in charge injection onto the floating gate. The charge is removed from the gate electrically or the memory cell is erased by exposing the device to ultraviolet radiation for a sufficient period of time. If the floating gate is covered by a silicon nitride layer, the floating gate will either not be able to be erased or the time period required to erase the floating gate will be dramatically increased, thereby reducing the effectiveness of the device.
SUMMARY OF THE INVENTION
Accordingly, a need has arisen for a semiconductor device architecture that allows for the use of silicon nitride as an etch stop within electronic devices but does not prevent the operation of memory systems that require ultraviolet radiation for erasability.
In accordance with the teachings of the present invention, a semiconductor device architecture is provided that substantially eliminates or reduces disadvantages associated with prior architectures and methods of construction.
In accordance with one embodiment of the present invention, a semiconductor device architecture is provided that comprises a floating gate formed outwardly from an outer surface of a semiconductor layer. A control gate is formed outwardly from the floating gate and separated therefrom by an interstitial insulator layer. The control gate and floating gate are covered by a silicon nitride encapsulation layer that comprises silicon nitride that exhibits a refractive index of less than 2.0 such that the transmittance of the silicon nitride material with respect to ultraviolet radiation is sufficient to allow for the erasure of charge stored on the floating gate by the radiation of the floating gate with ultraviolet radiation.
An important technical advantage of the present invention inheres in the fact that a silicon nitride etch stop layer can be used to completely encapsulate a gate structure for a flash memory or EEPROM device. The silicon nitride etch stop layer can be used to form the drain or bit line contact to the device and allows this contact to be spaced very close to the region occupied by the gate. Alternatively, the silicon nitride layer can be used to prevent the etching of the field oxide material surrounding the active moat area of an integrated device. This prevents the drain or bit line contact of a memory device from directly contacting the semiconductor substrate material within the active region of the device.
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Kaya Cetin
Lee Wei William
San Kemal Tamer
Brady III W. James
Dang Trung
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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