Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-10-18
2002-07-23
Dinh, Son T. (Department: 2821)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C257S612000, C257S712000, C257S714000, C257S720000, C257S722000
Reexamination Certificate
active
06423570
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and processes for packaging microelectronic dice. In particular, the present invention relates to a packaging technology that encapsulates a microelectronic die with an encapsulation material and utilizes a metallization layer to attach a heat spreader to the microelectronic die.
2. State of the Art
Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As these goals are achieved, microelectronic dice become smaller. Of course, the goal of greater packaging density requires that the entire microelectronic die package be equal to or only slightly larger (about 10% to 30%) than the size of the microelectronic die itself. Such microelectronic die packaging is called a “chip scale packaging” or “CSP”. However in such true CSP, the surface area provided by the microelectronic die active surface generally does not provide enough surface for all of the external contacts needed to contact the external component (not shown) for certain types of microelectronic dice (i.e., logic).
Additional surface area can be provided through the use of an interposer, such as a substrate (substantially rigid material) or a flex component (substantially flexible material).
FIG. 18
illustrates a substrate interposer
222
having a microelectronic die
224
attached to and in electrical contact with a first surface
226
of the substrate interposer
222
through small solder balls
228
. The small solder balls
228
extend between contacts
232
on the microelectronic die
224
and conductive traces
234
on the substrate interposer first surface
226
. The conductive traces
234
are in discrete electrical contact with bond pads
236
on a second surface
238
of the substrate interposer
222
through vias
242
that extend through the substrate interposer
222
. External contacts
244
(shown as solder balls) are formed on the bond pads
236
. The external contacts
244
are utilized to achieve electrical communication between the microelectronic die
224
and an external electrical system (not shown).
The use of the substrate interposer
222
requires number of processing steps. These processing steps increase the cost of the package. Additionally, even the use of the small solder balls
228
presents crowding problems which can result in shorting between the small solder balls
228
and can present difficulties in inserting underfilling between the microelectronic die
224
and the substrate interposer
222
to prevent contamination and provide mechanical stability.
FIG. 19
illustrates a flex component interposer
252
wherein an active surface
254
of a microelectronic die
256
is attached to a first surface
258
of the flex component interposer
252
with a layer of adhesive
262
. The microelectronic die
256
is encapsulated in an encapsulation material
264
. Openings are formed in the flex component interposer
252
by laser abalation through the flex component interposer
252
to contacts
266
on the microelectronic die active surface
254
and to selected metal pads
268
residing within the flex component interposer
252
. A conductive material layer is formed over a second surface
272
of the flex component interposer
252
and in the openings. The conductive material layer is patterned with standard photomask/etch processes to form conductive vias
274
and conductive traces
276
. External contacts are formed on the conductive traces
276
(shown as solder balls
278
surrounded by a solder mask material
282
proximate the conductive traces
276
).
Another problem arising from the fabrication of a smaller microelectronic dice is that the density of power consumption of the integrated circuit components in the microelectronic dice has increased, which, in turn, increases the average junction temperature of the dice. If the temperature of the microelectronic die becomes too high, the integrated circuits of the semiconductor die may be damaged or destroyed. Furthermore, for microelectronic dice of equivalent size, the overall power increases which presents the same problem of increased power density.
Thus, it may be necessary to attach a heat spreader to the microelectronic die.
FIG. 20
illustrates a heat spreader
288
attached to the microelectronic die
256
as shown in FIG.
19
. However, prior to attaching the heat spreader
288
to the microelectronic
256
, a back surface
286
of the microelectronic die
256
must be exposed. This is generally achieved by grinding away the back surface
284
.(see
FIG. 19
) of the encapsulation material
264
which can damage the microelectronic die
256
.
Therefore, it would be advantageous to develop new apparatus and techniques to expose the back surface of a microelectronic die for attachment of a heat spreader with potentially damaging the microelectronic die.
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patent: 5455457 (1995-10-01), Kurokawa
patent: 5497033 (1996-03-01), Fillion et al.
patent: 5514906 (1996-05-01), Love et al.
patent: 5527741 (1996-06-01), Cole et al.
patent: 5703400 (1997-12-01), Wojnarowski et al.
patent: 5745984 (1998-05-01), Cole, Jr. et al.
patent: 5895229 (1999-04-01), Carney et al.
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patent: 11045955 (1999-02-01), None
patent: 11312868 (1999-11-01), None
Ma Qing
Mu Xiao-Chun
Vu Quat T.
Dinh Son T.
Intel Corporation
Luu Pho
Winkle Robert G.
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