Semiconductor device and fabrication process thereof

Details Semiconductor device and fabrication process thereof Semiconductor device and fabrication process thereof

2000-11-20

2002-01-08

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000, C438S291000, C438S305000

Reexamination Certificate

active

06337249

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of the prior Japanese Patent application No. 6-289883 filed on Nov. 24, 1994, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an enhancement-type semiconductor device having an MIS (metal insulator semiconductor) structure and a fabrication process thereof, and relates, for example, to a ROM (read-only memory).
2. Related Arts
Heretofore, when structuring a mask ROM, an enhancement-type ROM transistor has been employed. Typically, a so-called ion-implantation type Rom is used wherein the threshold voltage is controlled by performing an ion implantation causing impurity ions to pass through a gate electrode to reach a channel region.
A fabrication process in a case for forming this ion-implantation type ROM using an N-channel transistor will be described with reference to
FIGS. 15A
through
15
D.
In an N-channel transistor, a P-type silicon monocrystalline substrate
11
is oxidized in an oxidizing atmosphere of, for example, oxygen gas, a mixed gas of H
2
O and oxygen gas, or the like, to form a gate-oxide film
12
, and thereabove is formed a gate electrode
13
of a polycrystalline silicon doped with, for example, a high concentration of phosphorus (FIG.
15
A).
Next, a film
14
which is an amorphous oxide film or nitride film is formed to an appropriate thickness over the entire surface of the wafer so that ions implanted during ion implantation which will be described later do not cause channeling of the polycrystalline silicon gate electrode
13
. Then, donor dopant (such as arsenic, phosphorus, or both) is implanted and a drain region
15
a
and source region
15
b
are formed (FIG.
15
B).
Thereafter, in order to create an enhancement-type ROM, a photoresist
16
is formed, and acceptor dopant such as boron, BF
2
, or the like is implanted in the channel region using the patterned photoresist as a mask to form a high-concentration P-type region
17
of higher doping concentration than the substrate
11
over the entirety of the channel region (FIG.
15
C).
Thereafter, a layer insulation film
18
composed of, for example, a BPSG film is formed over the entire surface, contact holes are formed in the layer insulation film
18
so as to reach the drain region
15
a
and source region
15
b
, respectively. Furthermore, a metal film of aluminum or the like is formed by a vapor deposition, sputtering, or chemical vapor growth process, and is patterned into a drain electrode
19
a
and source electrode
19
b
(FIG.
15
D).
An enhancement-type ROM is formed according to the foregoing. Memory functions as this ROM are performed by establishing the doping concentration of the high-concentration P-type region
17
. Additionally, in case this enhancement-type ROM is operated, the substrate
11
and source electrode
19
b
are set at, for example, 0 V, and the drain electrode
19
a
is set at 1 to 5 V. That is to say, the substrate
11
and source electrode
19
b
have the same; potential, and the drain electrode
19
a
is set at a higher potential.
SUMMARY OF THE INVENTION
However, in an enhancement-type ROM structure, as described above it is difficult to withstand voltage in a region of the channel region contiguous to the drain region
15
a
when compared when; ion implantation is not performed (i.e., when a high-concentration P-type region is not formed), this results in a problem in which leakage current from the drain region
15
a
to the substrate
11
or source region
15
b
is generated.
According to various investigations conducted by the inventors of the present application with respect to this problem, because a PN junction is defined between the e N-type drain region
15
a
of high concentration and the high-concentration P-type region
17
of the channel region and a high voltage of, for example, approximately 1 to 5 V with respect to the substrate
11
is applied to the drain region
15
a
, a Zener breakdown n or an avalanche breakdown occurs due to the foregoing PN junction, and thereby causing a large amount of leakage current becomes.
Moreover, the doping concentration of the high-concentration P-type region
17
formed on the entire surface of the channel region is on the order of 10
18
/cm
3
when, for example, the doping concentration of the substrate
11
is approximately 10
16
~10
17
/cm
3
and each doping concentration of the drain region
15
a
and source region
15
b
is approximately 10
20
/cm
3
.
Consequently, the higher the doping concentration of the high-concentration P-type region
17
of the channel region in order to increase threshold voltage in an enhancement-type ROM, the greater amount of leakage current is generated between the channel region and end portion of drain region
15
a
, and the more the withstand voltage declines. Power consumption also increases.
In light of the foregoing problems, it is an object of the present invention to suppress leakage current in a semiconductor device having an enhancement-type MOS structure.
To attain the object, the inventors devised forming the foregoing high-concentration P-type region
17
of the channel region not on the drain side, but from under the gate electrode to the source-region periphery in a semiconductor device having an enhancement-type MOS structure.
However, it was understood that even when a high-concentration P-type region is not formed on the drain region side, if an end portion of the high-concentration P-type region is proximate to an end portion of the drain region, leakage current does not decline sufficiently.
In regards to this structure when the operating voltage (for example 5 V) is actually applied to a transistor of enhancement-type MOS structure, a depletion layer expands from the PN junction between the drain region and channel region in accordance with the applied voltage, the depletion layer reaches the high-concentration P-type region and extends into the inside thereof, the electrical field intensity within the depletion layer increases sharply since it is difficult for the depletion layer to extend into the inside of a high-concentration region, the electrical field within the depletion layer becomes the critical field which causes avalanche breakdown or Zener breakdown even if the operating voltage is the maximum rated voltage, and thus leakage current is generated.
The present invention involves determining the position of the high-concentration P-type region so that, even if the depletion layer extending from the PN junction between the drain region and channel region reaches the high-concentration P-type region when operating voltage is applied, the electrical field within the depletion layer does not become the critical field which causes avalanche breakdown or Zener breakdown.
That is to say, a semiconductor device of MIS structure according to the present invention, which has a gate electrode formed on a semiconductor region with a gate insulation film interposed therebetween, source and drain regions making the semiconductor region therebetween a channel region, and a high-concentration region formed of the same conductivity type as the channel region and having a higher doping concentration than the channel region and disposed overlapping with the channel region, is characterized in that the high-concentration region is disposed remotely from at least the drain region, and that an end portion of the high-concentration region is established at a position such that an electrical field within a depletion layer which expands within the semiconductor region from a PN junction defined between the drain region and the semiconductor region toward the high-concentration region does not become the critical field causing avalanche breakdown or Zener breakdown when rated voltage of a time of actual usage is applied between the drain region and the semiconductor region.
Accordingly, when rated voltage is applied between the drain region and the semiconductor region,

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