Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-21
2002-09-10
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S387000, C438S397000, C257S303000, C257S308000, C257S309000
Reexamination Certificate
active
06448132
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a cylindrical memory cell which is provided a capacitor, and the method for the manufacture thereof.
2. Description of Related Art
The conventional method for manufacturing this type of semiconductor device will be explained with reference to
FIGS. 21 and 22
.
FIGS. 21 and 22
are schematic cross sectional views of the principal portion of a semiconductor device for explaining the conventional manufacturing process, respectively.
An interlayer insulating film
10
is formed on an appropriate semiconductor substrate
50
. A silicon nitride film
16
is formed on this interlayer insulating film
10
. A cell contact hole
12
is formed to pass through the silicon nitride film
16
and interlayer insulating film
10
; this cell contact hole
12
is filled with polysilicon to form a plug
14
. An underlying layer
18
is composed of the silicon nitride film
16
and the interlayer insulating film
10
, wherein the plug
14
is formed. A silicon dioxide film
28
is formed on the principal surface
18
a
of the underlying layer
18
. A resist film
32
is formed on the upper surface of the silicon dioxide film
28
. Photolithography is used to pattern this resist film
32
and a round opening is created as the capacitor pattern
34
(FIG.
21
(A)).
Next, the resist film
32
having formed therethrough the capacitor pattern
34
, is used as a mask and an isotropic etching is used to form a circular pocket or groove
38
in the silicon dioxide film
28
(FIG.
21
(B)). After the removal of the resist film
32
, a polysilicon film
40
is formed on the remaining silicon dioxide film
28
a
(FIG.
21
(C)). To provide the prescribed conductivity, impurities are dispersed in this polysilicon film
40
. In the pocket
38
, a polysilicon film
40
is formed on the pocket wall surface and pocket floor surface. A silicon dioxide film
42
is further deposited on the polysilicon film
40
(FIG.
21
(D)). Portions of the silicon dioxide film
42
outside of the pocket
38
are removed with a surface etch (or etching back) or with CMP (chemical mechanical polishing). Silicon dioxide film
42
a
is thereby left within the pocket
38
while the surface of the polysilicon film
40
is exposed (FIG.
22
(A))
The remaining silicon dioxide film
42
a
is used as a mask and a surface etch of the polysilicon film
40
is performed. This etch removes the portion of the polysilicon film
40
which is layered on the upper surface of the silicon dioxide film
28
a
. The polysilicon film
40
remains only on the pocket wall surface
38
b
and pocket floor surface
38
a
of the pocket
38
. The remaining polysilicon film
40
becomes a storage electrode
20
(FIG.
22
(B)). The silicon dioxide films
28
a
and
42
a
are then selectively removed by etching with hydrofluoric acid (HF), for example, with the silicon nitride film
16
acting as a stopper. Afterwards, a capacitor insulating film
22
is formed on the surface of the storage electrode
20
. A polysilicon film wherein impurities are dispersed is formed on the surface of the capacitor insulating film
22
to thereby form a cell plate electrode
24
(FIG.
22
(C)). In this way, a cylindrical memory cell, wherein the inner diameter of the storage electrode is essentially the same as the capacitor pattern
34
, is formed.
As memory cells have become smaller, capacitor patterns have becomes smaller, as have the capacitors formed thereby. Sufficient capacity cannot be attained with memory cells formed using the conventional method discussed above because the reduction in size has caused a reduction in capacitor area. To increase capacity, it is necessary to increase the height of the capacitor (height h shown in FIG.
22
(C)). This results in a large step between the memory cell portion and the surrounding circuit portions and makes photolithography difficult. Manufacturing memory cells with a high yield therefore becomes difficult.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device which is provided a capacitor with sufficient capacity and having a small difference in the levels of the memory cell portion and the surrounding area.
It is another object of the present invention to provide a method for manufacturing semiconductor devices, with which it is possible to form capacitors with sufficient capacity and without increasing the step between the memory cell portion and the surrounding area to a degree that makes photolithography difficult.
According to a first principal aspect of the present invention, there is provided a semiconductor device having the following constitution and which is provided a capacitor comprising first and second electrodes and a dielectric layer therebetween. The first electrode is formed as follows: an insulating film and resist film are formed on the principal surface of the underlying layer; photolithography is used to form a capacitor pattern in this resist film; the insulating film is etched with the mask being the resist film wherein this capacitor pattern is formed; a pocket is formed; and a conductive film is formed on the pocket wall surface and pocket floor surface of this pocket. This capacitor pattern is the first opening. The aperture area of this pocket is larger than the aperture area of the capacitor pattern. The aperture area of the second opening, delimited by the wall portion of the first electrode attained when a conductive film is formed on the pocket side walls, thereby becomes greater than the aperture area of the first opening.
Consequently, the aperture area of the pocket, wherein the conductive layer forming the first electrode is formed, is greater than the area of the capacitor pattern determined by the resolution of photolithography. The second opening of the first electrode is formed as a circle concentric to the first opening. The aperture area of the second opening is greater than the aperture area of the first opening.
In embodiments of the present invention, the aperture area of the second opening is preferably greater than the aperture area of the opening determined by the resolution limit of photolithography discussed above.
According to a second principal aspect of the present invention, there is provided a semiconductor device having the following constitution. In this semiconductor device, the aperture area of the pocket, at an intermediate vertical position located between the principal surface of the underlying layer and the upper surface of the insulating film, is greater than the aperture area of the capacitor pattern (first opening). The aperture area of the second opening, delimited by the middle of the wall portion of the first electrode attained when a conductive film is formed on the pocket side wall, thereby becomes greater than the aperture area of the first opening.
Consequently, at an intermediate position, at least, of the pocket wherein a conductive film to become the first electrode is layered, the aperture area i s greater than the area of the capacitor pattern determined by the photolithography resolution. The aperture area of the second opening of the first electrode can thereby be made greater than the aperture area of the first opening.
“In embodiments of the present invention, the wall portion of the first electrode may be at an angle to the principal surface so that the aperture area of the second opening increases as the distance upwards from the underlying layer increases.”
With such a constitution, the aperture area of the pocket, wherein the conductive film to become the first electrode is layered, becomes greater than the area of the capacitor pattern determined by the photolithography resolution.
In the preferred embodiments of the present invention, the lower portion may be at an angle to the principal surface so that the aperture area of the second opening, delimited by the lower portion of the wall portion, increases as the distance upwards from the underlying layer increas
Fahmy Wael
Oki Electric Industry Co. Ltd.
Volentine & Francos, PLLC
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