Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-29
2002-07-09
Wille, Douglas A. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S416000
Reexamination Certificate
active
06417038
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of fabricating a semiconductor device, and more particularly to such a method capable of fabricating CMOS semiconductor device in a smaller size and in a smaller number of steps.
2. Description of the Related Art
As a semiconductor device has been fabricated in higher integration, a concentration of impurities having an electrical conductivity opposite to an electrical conductivity of a channel region in a semiconductor substrate has been Ski increased in order to suppress short channel effect in MOS transistor.
In a surface-channel type transistor, as illustrated in
FIG. 1
, a threshold voltage is controlled by additionally introducing impurities having an electrical conductivity opposite to an electrical conductivity of a channel region, into a surface of a semiconductor substrate in the vicinity of the channel region.
However, in a transistor including a gate having a gate length of 0.5&mgr;m or smaller, impurities to be implanted into a substrate have to have a higher concentration in order to suppress short channel effect, resulting in that a threshold voltage becomes too high. Hence, as illustrated in
FIG. 2
, it would be necessary to reduce a concentration of impurities in a region in the vicinity of a surface of a semiconductor substrate.
However, ion-implantation and thermal diffusion have limitation in reducing a concentration of impurities in a region in the vicinity of a surface of a semiconductor substrate. Namely, it is quite difficult for conventional methods to reduce a threshold voltage down to 1V or smaller in a transistor including a gate having a gate length of about 0.1&mgr;m. If a threshold voltage could not be reduced down to 1V or smaller, a transistor could not make high-speed operation at a low voltage and at low power consumption.
In order to solve the above-mentioned problem, there has been suggested MOS transistor formed at a surface of a substrate with a layer containing impurities at a low concentration. Such MOS transistor is called a low-impurity channel transistor. For instance, Japanese Unexamined Patent Publications Nos. 59-222957, 60-211867, 61-32462, 63-169065, and 63-177470.
Japanese Unexamined Patent Publication No. 59-222957 has suggested a semiconductor device including a semiconductor substrate having a first electrical conductivity, an epitaxial layer formed on the substrate and having a second electrical conductivity, a first buried layer formed at an interface between the substrate and the epitaxial layer, and having the first electrical conductivity, a second buried layer formed at an interface between the substrate and the epitaxial layer, and having the second electrical conductivity, and a well layer extending from the epitaxial layer to the first buried layer. A first MOSFET having the second electrical conductivity is formed on the well layer, and a second MOSFET having the first electrical conductivity is formed on the epitaxial layer above the second buried layer.
Japanese Unexamined Patent Publication No. 60-211867 has suggested a semiconductor device including a p-type silicon substrate, an epitaxial layer formed on the p-type silicon substrate, n- and p-well regions formed in the epitaxial layer in contact with the p-type silicon substrate, NPN bipolar transistor formed on the n-type well region, and an n-channel MOS transistor formed on the p-type well region. The n- and p-well regions have a highly doped region at a bottom. A concentration of impurities decreases from the highly doped region towards a surface of the silicon substrate.
Japanese Unexamined Patent Publication No. 61-32462 has suggested a semiconductor device including a silicon substrate, first MOS transistor formed at a first electrical conductivity region of the silicon substrate and having a second electrical conductivity, a first low impurity layer formed at a surface of the silicon substrate and containing impurities at a concentration smaller than that of the first electrical conductivity region by an order or greater, a channel region of the first MOS transistor being formed on the first low impurity layer, second MOS transistor formed at a second electrical conductivity region of the silicon substrate and having a first electrical conductivity, and a second low impurity layer formed at a surface of the silicon substrate and containing impurities at a concentration smaller than that of the second electrical conductivity region by an order or greater, a channel region of the second MOS transistor being formed on the second low impurity layer.
Japanese Unexamined Patent Publication No. 63-169065 has suggested a insulating gate type field effect transistor including a semiconductor substrate, and an epitaxial layer formed at a surface of the semiconductor substrate. The epitaxial layer contains impurities at a concentration smaller than that of the semiconductor substrate, and has a thickness equal to or smaller than a width of a depletion layer to be formed in a channel region.
Japanese Unexamined Patent Publication No. 63-177470 has suggested a method of fabricating an insulating gate type field effect transistor, including - the step of forming an epitaxial layer at a surface of a semiconductor substrate by molecular beam epitaxy (MBE). The epitaxial layer is designed to contain impurity at a concentration smaller than that of the semiconductor substrate, and have a thickness equal to or smaller than 1000 angstroms. By forming the epitaxial layer, the field effect transistor could have an impurity profile in which a concentration of impurity varies in a step-like fashion in a depth-wise direction, and include a highly resistive active layer in a channel region.
Hereinbelow is explained a structure of a conventional low-impurity channel transistor with reference to
FIG. 3
, which is a cross-sectional view of an n-type transistor.
With reference to
FIG. 3
, a low-impurity channel transistor is comprised of a p-type silicon substrate (or a p-type well region)
1
, field oxide films
4
formed at a surface of the p-type silicon substrate
1
, a p-type silicon layer
51
containing impurity at a concentration smaller than that of the silicon substrate
1
by an order or greater, and acting as a channel region, source and drain regions
52
and
53
formed at a surface of the silicon substrate
51
around the p-type silicon layer
51
, and containing n-type impurity at a high concentration, a gate oxide film
6
formed on the p-type silicon layer
51
, and a gate electrode
7
formed on the gate oxide film
6
.
By designing the p-type silicon layer
51
to contain impurity at a relatively high concentration, it would be possible to prevent a depletion layer from extending from the drain region
53
to the source region
52
, resulting in that it is possible to suppress punchthrough.
When the above-mentioned conventional transistor is used for constituting CMOS transistor, NMOS and PMOS transistors in CMOS transistor have to be optimized. A substrate of NMOS transistor is usually designed to contain boron or boron compound such as BF
2
, and a substrate of PMOS transistor is usually designed to contain phosphorus or arsenic.
FIG. 4A
illustrates p-type impurity profile in NMOS transistor in a direction perpendicular to a surface of a substrate, and
FIG. 4B
illustrates n-type impurity profile in PMOS transistor in a direction perpendicular to a surface of a substrate. Boron contained in a substrate of NMOS transistor as a p-type impurity has a greater diffusion rate than that of phosphorus or arsenic contained in a substrate of PMOS transistor as an n-type impurity. Hence, after boron has been diffused and re-profiled by annealing to be carried out subsequently to formation of a low impurity layer at a surface of a substrate, a substrate of NMOS transistor contains boron at a surface thereof at a concentration greater than that of phosphorus or arsenic contained in a substrate of PMOS transistor.
For the above-mentioned reason, when CMOS transistor is to be fabri
Doan Theresa T.
Wille Douglas A.
Young & Thompson
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