Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-12
2002-05-21
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S486000, C438S530000
Reexamination Certificate
active
06391728
ABSTRACT:
FIELD OF THE INVENTION
The present specification relates generally to a method of fabricating an integrated circuit. More particularly, the present specification relates to a method of forming a highly localized halo profile to prevent punch-through.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. In such large ICs, the channel length of transistors, such as metal oxide semiconductor field effect transistors (MOSFETs) must be minimized. Minimization of the channel length allows greater number of transistors to be fabricated on a single substrate and also provides for a faster transistor switching speed due to the reduced capacitance and resistance between the source and the drain regions.
One of the major difficulties with reducing the channel length is “punch-through”, in which depletion layers from the source and drain regions contact one another, causing the potential barrier between the source and the drain to decrease. Punch-through results in significant leakage current, even when the transistor is in the off state.
The punch-through voltage (Vpt) of a device is defined as the drain-to-source voltage (Vds) at which the current from drain to source (Ids) reaches an unacceptable value with a gate-to-source voltage (Vgs) of zero. Punch-through is conventionally suppressed in a device to the point where Vpt is larger than any possible Vds. One method for suppressing Vpt is to increase the concentration of dopants in the drain and source regions to decrease the depletion layer widths. Typically, this increased concentration of. dopants is used along with a threshold voltage adjust (Vt-adjust) implant. A Vt-adjust implant is a region of increased doping, e.g. phosphorous in N-channel MOSFETs, boron in P-channel MOSFETs. Other dopants for the Vt-adjust implant can include indium and boron difluoride (BF
2
). The Vt-adjust implant is typically implanted beneath the channel region to raise the dopant concentration beneath the channel region above the dopant concentration of the substrate. However, during the subsequent thermal annealing process, the dopant from this Vt-adjust implant may diffuse toward the surface and raise the dopant concentration in the channel, causing carrier mobility degradation due to increased impurity scattering.
Another method for suppressing Vpt is using “halo” implants. P-type dopants (in N-channel MOSFETs) are implanted under the lightly doped drain/source extensions (e.g., tip regions of the drain and source regions.) The implanted dopant raises the doping concentration only on the walls of the source and drain regions near the surface channel region. Thus, the channel length can be decreased without needing to use a substrate doped to a higher concentration. However, “halo” implants must be fabricated with great precision and may also result in an increase in the sidewall junction capacitance.
Ideally, halo implants should be locally confined near the source/channel and the drain/channel junctions. The requirement of this tight confinement for halo implants is particularly important as the MOSFET channel length continues to shrink in size. In conventional CMOS fabrication processes, halo implants are implemented by ion implantation and subsequent thermal anneal activation. However, due to the transient enhanced diffusion (TED) effect, the dopant thermal diffusion is present, making the halo profile less confined.
Accordingly, there is a need for a method of forming highly localized halo profiles with greater precision. Further, there is a need for an improved method of suppressing punch-through in an integrated circuit. Even further still, there is a need for a method of forming halo implants after other thermal anneal processes are performed such that no additional thermal budget is added to the halo profile.
The teachings here and below extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
SUMMARY OF THE INVENTION
An exemplary embodiment relates to a method of forming halo regions in an integrated circuit. This method can include forming dummy spacer structures over an integrated circuit substrate proximate lateral side walls of a gate structure, providing an oxide layer over the integrated circuit substrate, removing the dummy spacer structures to create windows in the oxide layer exposing the integrated circuit substrate, providing an amorphization implant through the windows to form amorphous regions in the integrated circuit substrate, providing a halo dopant implant through the windows to the amorphous regions, and recrystallizating the amorphous regions in the integrated circuit substrate to form halo regions.
Another exemplary embodiment relates to a method of fabricating an integrated circuit which suppresses punch-through between a source and drain junction using a halo implant activated by a low temperature anneal. This method can include providing windows in an oxide layer-disposed over an integrated circuit substrate where the windows are located over a source and channel junction and a drain and channel junction in the integrated circuit substrate, using the windows to implant a species to create amorphous regions in the integrated circuit substrate proximate the source and channel junction and the drain and channel junction, using the windows to implant a halo dopant in the created amorphous regions, and activating the implanted halo dopant. The activated implanted-halo dopant forms halo regions localized near the source and channel junction and the drain and channel junction. The halo regions suppress punch-through effects.
Another exemplary embodiment relates to a method of forming a highly localized halo profile by a laser thermal process. This method includes forming an integrated circuit portion having source and drain regions in an integrated circuit substrate, a gate structure disposed between the source and drain regions, source and drain extensions extending from the source and drain regions to at least partially under the gate structure, and spacer structures located proximate lateral side walls of the gate structure and over the source and drain extensions. The method further includes depositing an oxide layer over the integrated circuit portion, removing the spacer structures, and forming halo regions localized in the integrated circuit substrate proximate the source and drain extensions. The halo regions have a halo dopant activated by recrystallization of an amorphous region.
Other features and advantages of embodiments of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5885886 (1999-03-01), Lee
patent: 5899719 (1999-05-01), Hong
patent: 6300205 (2001-10-01), Fulford et al.
patent: 63-78521 (1988-04-01), None
Advanced Micro Devices , Inc.
Chaudhari Chandra
Foley & Lardner
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