Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-21
2002-04-02
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S524000, C438S529000, C438S532000, C438S533000, C438S276000, C438S289000, C438S305000, C438S307000
Reexamination Certificate
active
06365463
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming transistors and, more particularly, to a method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up.
2. Description of the Related Art
The threshold voltage of a MOS transistor is the gate voltage that defines the boundary between the conducting and non-conducting states of the transistor. Gate voltages greater than the threshold voltage cause n-channel transistors to conduct (when an appropriate drain-to-source voltage is present), while p-channel transistors become non-conductive.
On the other hand, gate voltages less than the threshold voltage cause n-channel transistors to stop conducting, while p-channel transistors become conductive (when an appropriate source-to-drain voltage is present).
For long-channel transistors (transistors having a channel length greater than 2 um), the threshold voltage of a transistor can be accurately determined. The same models that are used to predict the threshold voltages of long-channel transistors, however, overstate the threshold voltages for short-channel transistors (the long-channel models typically ignore the effect of the source and drain depletion regions).
Specifically, the threshold voltages of short-channel n-channel transistors are less positive than predicted, while the threshold voltages of short-channel p-channel transistors are less negative than predicted. Thus, one of the effects of a short-channel device is a reduced threshold voltage.
The opposite effect, an increase or roll-up in the threshold voltages, occurs with sub-micron short-channel transistors which are fabricated with current-generation CMOS processes. For digital transistors, this roll-up effect causes few, if any, problems since the precise threshold voltage of digital transistors is typically not an issue. In some cases the roll-up can even increase manufacturing yields by raising the threshold voltages of devices that would otherwise have unacceptably low threshold voltages.
This is not the case, however, for high-precision analog transistors. High-precision analog circuits often rely on matched pairs of analog transistors for proper operation. Although two transistors can be formed to have nearly identical dimensions, most matched pairs of analog transistors have slight differences in length which, in turn, lead to slight degradations in the performances of the matched pairs. The threshold voltage roll-up accentuates these differences which further degrades the performances of the matched pairs.
In the paper by Alexander Kalnitsky et al., Suppression of the Vt Roll-Up Effect in Sub-Micron NMOST, 24th European Solid State Device Research Conference, Edinbougrh, 1994, the authors report that the threshold voltage roll-up effect is strongly related to the doping concentration of the polysilicon gates of the transistors.
SUMMARY OF THE INVENTION
The present invention provides a method that reduces the threshold voltage roll-up of a high-precision analog transistor, while also allowing the threshold voltage of a digital transistor to roll up. The method, which forms a device in a semiconductor material of a first conductivity type, begins by forming a layer of gate oxide on the semiconductor material. A layer of polysilicon is then formed on the layer of gate oxide.
Following this, the layer of polysilicon is selectively implanted with a dopant to dope the area where the gate of the analog transistor is to be formed. Next, the layer of polysilicon is etched to form a digital gate, an analog gate, and a plurality of exposed areas on the surface of the semiconductor material.
After the etch, the digital gate, the analog gate, and the exposed surface areas are implanted with a dopant to dope the digital gate, further dope the analog gate, and form source and drain regions adjacent to the digital gate and the analog gate.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.
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Kalnitsky, A., et al., “Suppression of the VT Roll-Up Effect in Sub-Micron NMOST,” 24th European Solid State Device Research Conference, Edinburgh, Scotland, (1994) pp. 377-380.
Bergemont Albert
Kalnitsky Alexander
National Semiconductor Corporation
Pillsbury Wintrop LLP
Wilczewski Mary
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