Semiconductor memory device having stable internal supply...

Details Semiconductor memory device having stable internal supply... Semiconductor memory device having stable internal supply...

2000-07-17

2002-04-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189110, C365S226000, C327S540000

Reexamination Certificate

active

06373754

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a stable internal supply voltage driver.
2. Description of the Related Art
As the integration density of semiconductor memory devices increases, the structure of supply voltage generating means of a memory cell array is very important. Namely, various problems are caused since a plurality of memory cell arrays simultaneously operate. In particular, when the memory cell array operates, a supply voltage generating apparatus for supplying power to the memory cell array must simultaneously supply a large amount of charge. Accordingly, noise can be generated in the power supply. Therefore, in general, in order to make up for a deficiency in charge, the supply voltage generating apparatus is operated by feeding back a supply voltage to the supply voltage generating apparatus. However, in this case, since chips become large, operation speed is reduced.
FIG.
1
. is a schematic block diagram of a semiconductor memory device having a conventional internal supply voltage driving scheme.
Referring to
FIG. 1
, the conventional semiconductor device includes a memory cell array block
101
, a differential amplifier
103
using an internal supply voltage MIVC, which are fed back from the memory cell array block
101
, and a reference voltage VREF, and an internal supply voltage driver
105
for driving an internal supply voltage IVC in response to the output of the differential amplifier
103
. The internal supply voltage IVC is generated by an internal supply voltage generating apparatus, which is not shown.
However, in the semiconductor memory device having the conventional internal supply voltage driving scheme, when the size of the memory cell array block
101
is large, that is, when the number of bit line pairs BL and {overscore (BL)} to be sensed at one time is large, a large amount of current is consumed by the memory array block
101
during a sensing operation. Accordingly, a severe dip
201
phenomenon occurs in the output N
1
of the internal supply voltage driver
105
, as shown in FIG.
2
. The dip phenomenon produces a bad effect on parameters related to the speed of the semiconductor memory device. Also, the semiconductor memory device may mis-operate due to the noise caused by the dip phenomenon.
Therefore, in the conventional semiconductor memory device, the differential amplifier
103
is driven by the internal supply voltage MIVC fed back from the memory cell array block
101
and the internal supply voltage driver
105
is driven by the output of the differential amplifier
103
, so that the dip phenomenon is reduced. However, in this case, it is difficult to sufficiently prevent the dip
201
phenomenon since it takes time to feed back the internal supply voltage MIVC. Also, an overshooting
202
phenomenon may occur in the output N
1
of the internal supply voltage driver
105
, as shown in
FIG. 2
, after the internal supply voltage driver
105
is driven, due to a delay time until the internal supply voltage MIVC is fed back.
SUMMARY OF THE INVENTION
In order to solve the above problems, it is an object of the present invention to provide a semiconductor memory device, in which the output of an internal supply voltage driver is stable.
To achieve the above object, according to an aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell array block, a differential amplifier, using a reference voltage and an internal supply voltage fed back from the memory cell array block as inputs, an internal supply voltage driver for supplying an internal supply voltage to the memory cell array block in response to the output of the differential amplifier, a pull down circuit for pulling down the output port of the differential amplifier in response to a control signal having a predetermined pulse, and a control signal generating circuit for generating the control signal in response to an input signal transited during a sensing operation of the memory cell array block.
The control signal generating circuit is a pulse generating circuit for generating the control signal having a positive pulse in response to the input signal.
According to another aspect of the present invention, there is provided a semiconductor memory device, comprising a memory cell array block, a differential amplifier, using a reference voltage and an internal supply voltage fed back from the memory cell array block as inputs, an internal supply voltage driver for supplying an internal supply voltage to the memory cell array block in response to the output of the differential amplifier, a pull up circuit for pulling up the output port of the differential amplifier in response to a control signal having a predetermined pulse, a delay circuit for delaying an input signal transited during the sensing operation of the memory cell array block for a predetermined time and outputting the delayed input signal, and a control signal generating circuit for generating the control signal in response to the output signal of the delay circuit.
The control signal generating circuit is a pulse generating circuit for generating the control signal having a negative pulse in response to the input signal.


REFERENCES:
patent: 5689460 (1997-11-01), Ooishi
patent: 5982162 (1999-11-01), Yamauchi
patent: 6046624 (2000-04-01), Nam et al.
patent: 6163180 (2000-12-01), Hidaka et al.

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