Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-06-30
2002-03-05
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S729000, C714S738000
Reexamination Certificate
active
06353905
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a test facilitation technique incorporated into a semiconductor integrated circuit, and to a technique effective for application to a semiconductor integrated circuit in which, for example, JTAG (Joint Test Action Group) has been adopted as a boundary scan standard.
As a test facilitation technique used for a semiconductor integrated circuit, a structure has been widely adopted which performs a test operation while a scan path is caused to transfer scan data in synchronism with a scan clock upon the test operation, and scans out the result thereof.
Japanese Patent Application Laid-Open No. Hei 3-42850 has described an invention wherein when a test mode is specified or designated from the outside of a semiconductor integrated circuit, scan data is automatically generated thereinside and thereby a burn-in test is allowed through a scan path. An invention has been described in Japanese Patent Application Laid-Open No. Hei 6-201780, wherein a test pattern generator is placed at the input of a scan chain and a test output compressor is placed at the output of the scan chain, whereby the shortening of a test time interval is set up. Japanese Patent Application Laid-Open No. Hei
5-264664
has described a technique related to boundary scan using a TAP controller and wherein a clock is supplied only to each of registers to be tested in accordance with the result of decoding of an instruction issued from the TAP controller, thereby achieving low power consumption.
Japanese Patent Application Laid-open No. Hei 5-264664 has disclosed a description related to an invention wherein a test enable signal and a test clock signal are respectively supplied in parallel to a plurality of semiconductor integrated circuits each having a self-test circuit incorporated therein and self-test mechanisms are simultaneously operated to carry out troubleshooting, whereby a test time interval is shortened. Japanese Patent Application Laid-Open No. Hei 8-220192 has disclosed a description related to an invention wherein inspection control LSI is implemented on a single circuit printed board together with a plurality of tested LSI which are addressed and have chains of scannable flip-flop respectively, and the inspection control LSI has a pseudo-random number generator and a code compressor and writes a pseudo random number into its corresponding flip-flop upon scan-in and supplies data of each flip-flop to the code compressor upon scan-out, thereby making it possible to achieve the facilitation and speeding up of troubleshooting.
SUMMARY OF THE INVENTION
The present inventors have investigated or discussed a device test on a semiconductor integrated circuit equipped with a plurality of pieces of circuit modules (corresponding to functional units also called functional modules) relatively large in logic scale as in a memory, a CPU or the like. According to the result of discussions, they have revealed the necessity for reducing the amount of test data to be supplied from the outside and the amount of data about test results to be outputted to the outside and parallelizing test operations for circuit modules to thereby shorten test times with a view toward improving the efficiency of testing. In order to reduce a logical and physical scale of a circuit necessary for testing to the utmost, a circuit for performing the input and output of test data and result data to and from the respective circuit modules needs to be shared between the respective circuit modules. Further, when JTAG is adopted as the standard for boundary scan for inspecting an electrical connection between a semiconductor integrated circuit to which a surface mounting package like BGA (Ball Grid Array) is applied, and a printed circuit board, such a JTAG controller as used for the boundary scan alone is appropriated to other tests. Thus, this will be useful to reduce the logical and physical scale of the test circuit. Any prior art will not be enough for these points.
An object of the present invention is to provide a semiconductor integrated circuit capable of reducing the amount of test data to be supplied from the outside and the amount of data about test results to be outputted to the outside in order to test a plurality of circuit modules, and shortening the time required to test the plurality of circuit modules.
Another object of the present invention is to provide a semiconductor integrated circuit wherein the scale of a test circuit required to test a plurality of circuit modules can be reduced as small as possible.
A further object of the present invention is to provide design data capable of facilitating the design of a semiconductor integrated circuit which implements the shortening of a test time and a reduction in the scale of a test circuit.
The above, and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Summaries of typical ones of the inventions disclosed in the present application will be described in brief as follows:
[1] A semiconductor integrated circuit comprises a single semiconductor chip including a plurality of circuit modules each provided with a test input terminal, a test output terminal and a test control terminal, a test path which connects the test output terminal of one circuit module to the test input terminal of the other circuit module to thereby form a test signal chain, and a test interface circuit connected to the test path. Each circuit module has a tested circuit, a test register circuit and a test control circuit. The test register circuit is connected to the test path through the test input terminal and the test output terminal and permits input and output to and from the test control circuit. The test control circuit receives a start for a test on the tested circuit from the test control terminal to thereby perform the test using test control information outputted from the test register circuit and supplies information about the result of test to the test register circuit. The test interface circuit supplies the test control information to the test register circuit from the outside through a test path and outputs the information about the result of test from the test register circuit to the outside through the test path.
When each of the tested circuits is tested, test control information can be externally inputted to a test interface circuit, and the test control information can be set to each of the test register circuits in all the circuit modules to be tested, through a test path corresponding to a test signal chain from the test interface circuit. Thereafter, when an instruction for a test operation is given to each of the test control circuits through a control terminal, a test circuit allows the tested circuits to be tested based on the test control information on a parallel basis. Information about test results are held in each individual test register circuits. Afterwards, the information held in the test register circuits in all the circuit modules to be tested are read into the test interface circuit through the test path corresponding to the test signal chain and outputted to the outside. Thus, the test operations for the circuit modules can be parallelized and hence a test time interval can be shortened. Since the test interface circuit, which performs the input and output of the test control information and test result data to and from the circuit modules, can be shared between the respective circuit modules, this can contribute even to a reduction in logical/physical scale of a circuit necessary for testing.
[2] A test pattern generator and a compressor may be adopted for the test control circuit. The test pattern generator generates a test pattern for each test circuit, based on the test control information inputted to the test register circuit. The compressor compresses the result of operation of the tested circuit to thereby generate information about the result of test and supplies the same to
De'cady Albert
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
Torres Joseph
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