Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-11-20
2002-01-08
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230060, C326S083000, C327S108000
Reexamination Certificate
active
06337811
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, for example, to a circuit for improving the output characteristics of an output stage of a semiconductor device, Particularly, the present invention relates to a semiconductor device having a semiconductor element referred to as an open drain, an open collector or the like which becomes operable when connected to an external power source.
BACKGROUND ART
An open drain is conventionally known and used as an output stage of the above type of semiconductor device. For example, as shown in
FIG. 11
, such a semiconductor device has a structure in which the source of an N-type MOS transistor
10
constituting the output stage is connected to the ground, and the drain thereof in connected to a pad
20
which is an electrode used for external connection. In the semiconductor device having such a structure, a second power source potential VDD
2
independent of a first power source potential VDD
1
to be supplied to the inside of the semiconductor device is applied to the pad
20
via a pull-up resistor
30
. A signal from a circuit (not shown) preceding a buffer circuit
40
is applied to the gate of this N-type MOS transistor
10
via the buffer circuit
40
. The buffer circuit
40
operates by the supply of the first power source potential VDD
1
.
However, the following problem exists in the conventional devices having the above structure.
Specifically, when the first power source potential VDD
1
to be supplied to the inside of the semiconductor device is shut off, the buffer circuit
40
becomes non-operational. For this reason, normally, the potential of an output line
42
of the buffer circuit
40
connected to the gate of the N-type MOS transistor
10
should become zero to make the MOS transistor
10
nonconductive. The potential of the pad
20
would be thereby held at the second power source potential VDD
2
. However, the potential of the output line
42
does not become zero in actual operation and the MOS transistor
10
becomes incompletely nonconductive. This brings about the problem that the potential of the pad
20
is not maintained at the second power source potential VDD
2
.
For example, if the potential of the pad
20
is not raised to the second power source potential VDD
2
and another semiconductor chip is connected through the pad
20
, the current may flow from the circuits of other semiconductor chips into the MOS transistor
10
.
The inventor has directed his attention to fact that the above problem is caused because the potential of the output line
42
is not lowered sufficiently to make the MOS transistor
10
completely nonconductive due to parasitic capacitance and the like in a semiconductor substrate even if the supply of the first power source potential VDD
1
is shut off, and achieved the present invention.
DISCLOSURE OF THE INVENTION
An objective of the present invention is to provide a semiconductor device which can reliably switch the operating state of a transistor to which a second power source potential is supplied according to the state of supply of a first power sources potential.
Another objective of the present invention is to provide a semiconductor device which can reliably switch the operating state of a transistor which is used as an open drain or open collector.
A further objective of the present invention is to provide a semiconductor device which can improve the operational reliability of an output stage thereof.
According to an aspect of the present invention, there is provided a semiconductor device according comprising:
a buffer circuit which is operated by supply of a first power source potential;
a transistor which is provided on a supply line of a second power source potential and has a gate connected to an output line of the buffer circuit; and
a potential setting circuit which sets a potential of the output line of the buffer circuit to a level lower than the threshold level of the transistor, when the supply of the first power source potential is shut off.
In this aspect of the invention, when the supply of the first power source potential is shut off, the potential of the output line of the buffer, that is, the potential between the gate and source of the transistor is set to a level lower than the threshold level of the transistor. As a result of this, the transistor can be reliably made non-operational. Therefore, in contrast to the conventional art, the occurrence of such an event that the transistor becomes nonconductive only incompletely although the supply of the first power source potential in shut off can be reliably avoided.
The transistor may be an N-type MOS transistor. As an example of a case using an N-type MOS transistor, there is a case where the semiconductor device comprises a pull-up resistor and a pad to which the second power source potential is supplied through the pull-up resistor. In this case, the N-type MOS transistor is connected between the pad and a ground. In the case using the N-type MOSFET, the potential setting circuit may preferably set the potential of the output line of the buffer circuit to the ground potential when the supply of the first power source potential in shut off. This makes it possible to make the N-type MOS transistor completly nonconductive.
Preferred examples of the potential setting circuit will be described below.
The potential setting circuit may have a firs N-type MOS transistor and a second N-type MOSTET which are connected in parallel between the output line of the buffer circuit and the ground. The first N-type MOS transistor has a gate connected to the output line of the buffer circuit, and the second N-type transistor has a gate connected to the pad.
In this example, the first N-type MOS transistor functions as a diode forward-connected between the output line of the buffer circuit and the ground. Therefore, the potential of the output line of the buffer circuit can be reliably dropped to the threshold level of the first N-type MOSFET by the first N-type MOS transistor when the supply of the first power source potential is shut off. If the potential of the output line of the buffer circuit is designed to be equal to or less than the threshold level of the first N-type MOSFET, the N-type MOS transistor can be made nonconductive. And then if the potential of the pad is increased to a level equal to or higher than the threshold level of the second N-type MOS transistor, the second N-type MOS transistor becomes conductive. As a result, the potential of the output line of the buffer can be dropped to the ground potential.
In another example, the potential setting circuit may have a P-type MOS transistor connected between the output line of the buffer circuit and the ground The first power source potential may be supplied to a gate of the P-type MOS transistor. In this case, when the supply of the first power source potential is shut off, the P-type MOS transistor becomes conductive and the potential of the output line of the buffer circuit can be reliably dropped to the threshold level of the P-type MOS transistor. If the potential of the output line of the buffer circuit is made to a level equal to or less than the threshold level of the N-type MOS transistor, the N-type MOS transistor can be made nonconductive.
In a further example, the potential setting circuit may have a first N-type MOS transistor connected between the output line of the buffer circuit and the ground, and a potential applying circuit which applies a potential sufficient to take the first N-type MOS transistor conductive to a gate of the first N-type MOS transistor, when the supply of the first power source potential is shut off. The potential applying circuit may have: a second N-type MOSFET, a P-type MOS transistor, and a third N-type MOS transistor which are connected in series between a supply line of the first power source potential and the ground; and a capacitance connected between the ground and wiring for connecting the second N-type MOS transistor to the P-type MOS transistor. In this case, gates of the second N-typ
Auduong Gene N.
Nelms David
Oliff & Berridg,e PLC
Seiko Epson Corporation
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