Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-31
2002-07-23
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S313000, C438S330000, C438S238000
Reexamination Certificate
active
06423593
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a process for manufacturing the same. More particularly, the present invention relates to a technique that can be effectively applied to a structure comprising an insulating film having a hole (recess) and a metal film formed in the hole and containing Ru (ruthenium) as principal ingredient and also to a process for manufacturing such a structure.
BACKGROUND OF THE INVENTION
A DRAM comprises a MISFET for memory cell selection and an information storage capacity element connected in series to the MISFET. The information storage capacity element is typically formed by sequentially depositing silicon for forming a lower electrode, tantalum oxide for forming a capacity insulating film and silicon for forming an upper electrode.
The information storage capacity element is formed in a deep hole that is formed in insulating film in order to downsize the element and, at the same time, secure a certain degree of capacity.
SUMMARY OF THE INVENTION
However, when silicon is used for the lower electrode, a silicon oxide nitride film is formed along the interface of the silicon and the oxide tantalum deposited thereon in the heat treatment process conducted (at 800° C. for 3 minutes in an oxidizing atmosphere) for the purpose of crystallizing and improving the film quality of the tantalum oxide. Therefore, while the tantalum oxide and the silicon oxide nitride film operate as dielectric to suppress any possible leak currents, it is difficult to make them show a high dielectric constant.
Additionally, as device is down-sized, the hole for forming the information storage capacity element also needs to be down-sized and eventually the undulations of crystallized silicon on the wall of the hole come to contact each other so as to eliminate any room for forming upper film layers such as the tantalum oxide film.
The inventors of the present invention have been engaged in research and development for materials that can be used for the lower electrode of an information storage capacity element. They are currently looking into the feasibility of using ruthenium (Ru) for the lower electrode in order to dissolve the above identified problems.
Ru does not form a low dielectric constant film such as oxide nitride film and can be used to form a thin film because it is metal.
However, in an experiment using an Ru film for the lower electrode, there appeared a phenomenon where the film thickness was large in an upper part of the side wall of the hole and was small on the bottom of the hole as shown in FIG.
25
A. When such an Ru film is subjected to heat-treatment to improve the density thereof, the thin Ru film on the bottom of the hole can agglomerate to produce islands of Ru (FIG.
25
B). Then, the Ru film is discontinued and can no longer operate as lower electrode.
On the other hand, when the Ru film on the bottom of the hole is made to show a large film thickness in order to secure the continuity thereof, the Ru film in the upper part of the side wall of the hole is increased accordingly until it contact itself to eliminate any room for forming upper film layers including a tantalum oxide film (FIG.
26
).
Thus, it is an object of the present invention to provide a technique with which an Ru film can be formed effectively and efficiently in a hole for the lower electrode of an information storage capacity element.
Another object of the invention is to provide a technique with which a desired Ru film can be formed to improve the performance of an information storage capacity element.
These and other objects and the novel features of the present invention will become apparent from the following description made by referring to the accompanying drawings.
In an aspect of the invention, there is provided a process for manufacturing a semiconductor integrated circuit device comprising:
(a) a step of forming a MISFET for memory cell selection on the main surface of a semiconductor substrate;
(b) a step of forming a plug electrically connected to the source/drain region of said MISFET for memory cell selection;
(c) a step of forming a silicon oxide film on said plug;
(d) a step of forming a hole getting to the surface of said plug in said silicon oxide film;
(e) a step of forming an Ru film on the side wall and the bottom of said hole by causing an organic compound of Ru and an oxidizing agent, the gasification flow rate of the organic compound of Ru being not less than 5% of the flow rate of the oxidizing agent;
(f) a step of forming a capacity insulating film on said Ru film; and
(g) a step of forming an upper electrode on said capacity insulating film.
Preferably, the reaction of said organic compound of Ru and said oxidizing agent is conducted at temperature not higher than 300° C.
In another aspect of the invention, there is provided a semiconductor integrated circuit device comprising:
(a) a MISFET for memory cell selection formed on the main surface of a semiconductor substrate;
(b) a plug electrically connected to the source/drain region of said MISFET for memory cell selection;
(c) a silicon oxide film formed on said plug;
(d) a hole formed in said silicon oxide film and extending to the surface of said plug; said hole having a depth not less than five times of the short diameter thereof;
(e) a information storage capacity element comprises an Ru film formed in said hole, a capacity insulating film formed in on the Ru film and an upper electrode formed on the capacity insulating film;
the film thickness of the Ru film on the bottom of the hole being not less than 50% of the largest film thickness thereof in the hole.
Preferably, said hole has a depth of about 250 nm.
Preferably, an adhesive layer is formed between said Ru film and said silicon oxide film.
Preferably, said adhesive layer is made of tantalum oxide.
Preferably, the surface undulations of said Ru film are not greater than 5 nm.
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patent: 5973351 (1999-10-01), Kotecki et al.
patent: 6057081 (2000-05-01), Yunogami et al.
patent: 6215144 (2001-04-01), Saito et al.
patent: 6235572 (2001-05-01), Kunitono et al.
patent: 6258649 (2001-07-01), Nakamura et al.
patent: 6326218 (2001-12-01), Yunogami et al.
Iijima Shinpei
Yamamoto Satoshi
Antonelli Terry Stout & Kraus LLP
Chaudhuri Olik
Hitachi , Ltd.
Schillinger Laura M
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