Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-28
2002-09-17
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S275000, C438S311000
Reexamination Certificate
active
06451656
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to semiconductor-on-insulator (SOI) integrated circuits and, more particularly, to an inverter made from a double gate MOSFET and method of making a semiconductor line for the inverter.
BACKGROUND ART
Traditional semiconductor-on-insulator (SOI) integrated circuits typically have a silicon substrate having a buried oxide (BOX) layer disposed thereon. A silicon active layer is disposed on the BOX layer. Within the active layer, active devices, such as transistors, are formed in active regions. The size and placement of the active regions are defined by isolation regions. As a result of this arrangement, the active devices are isolated from the substrate by the BOX layer. More specifically, a body region of each SOI transistor does not have body contacts and is therefore “floating.”
SOI chips offer potential advantages over bulk chips for the fabrication of high performance integrated circuits for digital circuitry. Such digital circuitry is typically made from partially-depleted metal oxide semiconductor field effect transistors (MOSFETs). In such circuits, dielectric isolation and reduction of parasitic capacitance improve circuit performance, and virtually eliminate latch-up in CMOS circuits. In addition, circuit layout in SOI can be greatly simplified and the packing density greatly increased.
However, there exists a need in the art to efficiently fabricate logical circuit elements, such as inverters, from SOI active devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, the invention is a method of forming a semiconductor line from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer.
According to another aspect of the invention, the invention is a method of forming a double gate metal oxide semiconductor field effect transistor (MOSFET) from a semiconductor-on-insulator (SOI) wafer, the SOI wafer having a substrate with a buried oxide (BOX) layer disposed thereon and a semiconductor active layer disposed on the BOX layer. The method includes the steps of forming a semiconductor line, the step of forming the semiconductor line comprising the steps of (a) forming a dummy island on the active layer; (b) forming a sidewall spacer adjacent the dummy island; (c) removing the dummy island; (d) removing semiconductor material of the active layer left exposed by the sidewall spacer; and (e) removing the sidewall spacer; and forming a gate line disposed on the semiconductor line, the gate line overlapping the semiconductor line in at least two places.
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En William G.
Yu Bin
Advanced Micro Devices , Inc.
Pham Long
Renner , Otto, Boisselle & Sklar, LLP
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