Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-06-30
2002-07-02
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S778000, C257S787000, C257S698000, C257S782000, C257S784000
Reexamination Certificate
active
06414391
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays. The ball grid array packages may be stacked on flexible or rigid substrates.
2. State of the Art
Chip on board technology generally consists of three types of techniques for attaching a semiconductor device to a printed circuit board, such as flip chip attachment, wirebonding, and tape automated bonding techniques.
Flip chip attachment consists of attaching a semiconductor device, generally having a ball grid array (BGA), a slightly larger than integrated circuit carrier (SLICC), or a pin grid array (PGA) to a printed circuit board. With the BGA or SLICC, the solder ball arrangement on the semiconductor device must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connections are made. The semiconductor device is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor device must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor device is generally bonded by soldering the pins into place. An underfill encapsulant is generally disposed between the semiconductor device and the printed circuit board to prevent contamination. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J's are soldered to pads on the surface of the circuit board. However, the lead and pad locations must coincide, as with the other types of flip-chip techniques.
Wirebonding and tape automated bonding (TAB) attachment generally begin with attaching a semiconductor device to the surface of a printed circuit board with an appropriate adhesive. In wirebonding, a plurality of bond wires is attached, one at a time, from each bond pad of the semiconductor device to a corresponding lead on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques, such as ultrasonic bonding, using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld, thermocompression bonding, using a combination of pressure and elevated temperature to form a weld, and thermosonic bonding, using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor device may be oriented having either the active surface up or the active surface down (with the bond pads thereon either up or down with respect to the printed circuit board) for wire bonding, although active surface up is the most common. With TAB, metal tape leads are attached between the bond pads on the semiconductor device and the leads on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Although such methods are effective for bonding semiconductor devices to printed circuit boards, the terminal arrangements of the devices and the connection arrangements of the boards must be designed to accommodate one another. Thus, it may be impossible to electrically connect a particular semiconductor device to a printed circuit board for which the semiconductor device terminal arrangements were not designed to match the board's connection arrangement. With either wirebond or TAB attachment, the semiconductor device bond pad arrangement may not correspond to the lead ends on the circuit board, making attachment difficult due to the need for overlong wires and the potential for inter-wire contact and shorting. With flip chip attachment, if the printed circuit board connection arrangement is not a mirror-image of the solder ball or pin arrangement of the semiconductor device, electrically connecting the flip chip to the printed circuit board is impossible.
Ball grid array (BGA) semiconductor device packages are well known in the art. A BGA package typically comprises a substrate, such as a printed circuit board, with a semiconductor device, such as a dynamic random access memory device, mounted on the top side of the substrate. The semiconductor device has a plurality of bond pads on the active surface thereof electrically connected to a series of metal traces on the top surface or top side of the printed circuit board. The connection between the bond pads and the metal traces is provided by wire bonds electrically and mechanically connecting the semiconductor device and the printed circuit board. The series of metal traces on the printed circuit board is connected, in turn, to a second series of metal traces on the bottom surface or bottom side of the printed circuit board using a series of vias extending therethrough. The second series of metal traces each terminate with a connection contact pad where a conductive element is attached. The conductive elements can be solder balls or conductive filled epoxy. The conductive elements are arranged in an array pattern and the semiconductor device and wire bonds are encapsulated with a molding compound.
As semiconductor device and grid array densities increase, the desire in packaging semiconductor devices has been to reduce the overall height or profile of the semiconductor package. The use of BGA's has allowed for this reduction of profile as well as increased package density. Density has been increased by using lead frames, such as lead-over-chip type lead frames, in an effort to increase the semiconductor device density as well as allow stacking of the semiconductor devices one on top another.
One example of a lead chip design in a BGA package is shown in U.S. Pat. No. 5,668,405. A semiconductor device is disclosed having a lead frame attached to the semiconductor device. Through holes are provided that allow for solder bumps to connect via the lead frame to the semiconductor device. Such a mounting arrangement requires several steps for attaching the semiconductor device to the lead frame, then providing sealing resin, and subsequently adding a base film and forming through holes in the base film. A cover resin is added before solder bumps are added in the through holes to connect to the lead frame. This particular structure lacks the ability to stack semiconductor devices one on top another.
U.S. Pat. No. 5,677,566, commonly assigned to the assignee of the present invention, illustrates a semiconductor device package that includes discrete conductive leads with electrical contact bond pads on a semiconductor device. The lead assembly is encapsulated with a typical encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit. The semiconductor device has the bond pads located in the center of the active surface of the device, thus allowing the conductive leads to be more readily protected once encapsulated in the encapsulating material. However, the assembly illustrated in the '566 Patent lacks the ability to stack one semiconductor device on top another.
U.S. Pat. No. 5,625,221 illustrates a semiconductor device package assembly that has recessed edge portions that extend along at least one edge portion of the assembly in an attempt to form a stacked package of semiconductor devices. An upper surface lead is exposed therefrom and a top recess portion is disposed on a top surface of the assembly. A bottom recess portion is disposed on the bottom surface of the assembly such that when the assembly is used in fabricating a three-dimensional integrated circuit module, the recess edge portion accommodates leads belonging to an upper semiconductor assembly to provide electrical interconnection therebetween. However, the assembly requires long lead wires from the semiconductor chip to the outer edges. These lead wires add harmful inductance and unnecessary signal delay and can form a weak link in the electrical interconnection between the semiconductor device and the out
Corisis David J.
Kinsman Larry D.
Mess Leonard E.
Moden Walter L.
Abraham Fetsum
TraskBritt
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