Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-08-16
2002-09-03
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S981000
Reexamination Certificate
active
06444528
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to field effect transistors, and in particular to trench transistors and methods of their manufacture.
FIG. 1
is a simplified cross section of a portion of a conventional trench power metal-oxide-semiconductor field-effect transistor (MOSFET). A trench
10
has sidewalls
11
and bottom
17
, and is lined with an electrically insulating material
12
that acts as a gate dielectric. Trench
10
is filled with a conductive material
15
, such as polysilicon, which forms the gate of the transistor. The trench, and hence the gate, extend from the surface of the silicon into the substrate down through a body region
22
and into a drain region
16
. In the example shown in
FIG. 1
, the body region
22
is a P-type region and the drain region
16
is an N-type region. Drain region
16
may be electrically contacted through the substrate of the device. N-type regions
14
adjacent to and on opposite sides of the trench
10
form the source electrode
18
of the transistor. An active channel region
20
is thus formed alongside of the trench between the N-type regions
14
of the source electrode
18
and the drain region
16
.
An important parameter in a trench power MOSFET is the total gate charge. In some applications of conventional trench power MOSFETs, such as DC-DC converters, the lower the gate charge the better the efficiency of the overall design. One major component of the total gate charge is the charge required to supply what is known as the Miller capacitance, which is a parasitic capacitance that forms between the gate and the drain. The Miller capacitance is an effective increase of gate to drain capacitance effect due to a rising drain current in the MOSFET active state. As a result, a higher proportion of the total gate charge flows through the gate-drain capacitance, and the rate of the rise of the gate to drain voltage is reduced, causing negative feedback from the drain circuit to the gate circuit. Thus, an effective way to lower the gate charge is to reduce the Miller Capacitance. One method to decrease the Miller Capacitance is to increase the thickness of the gate dielectric. However a uniformly thicker gate dielectric layer requires higher gate charge, which can detrimentally affect the electrical performance of the transistor.
SUMMARY OF THE INVENTION
The present invention provides a trench metal oxide semiconductor field effect transistor (MOSFET) having a dielectric layer that is thicker at the bottom of the trench as compared to the dielectric layer on the sidewalls of the trench where the transistor channel is formed.
Accordingly, in one embodiment, the present invention provides for gate isolation structure of a semiconductor device that includes a trench in a silicon substrate, and a gate isolation layer formed on sidewalls and bottom of the trench, where the gate isolation layer has a first thickness on the sidewalls and a second thickness at the bottom that is greater than the first thickness.
In another embodiment, the invention provides a method of forming a gate dielectric layer of trench field-effect transistor. The method includes the steps of forming a trench in a silicon substrate, growing a thermal oxide layer on the sidewalls and bottom of the trench, etching away the thermal oxide layer from the bottom of the trench to expose the silicon substrate, and depositing a selective oxide layer at the bottom of the trench over the silicon substrate to a desired thickness, wherein the desired thickness is greater than a thickness of the thermal oxide layer on the sidewalls of the trench.
In another embodiment, the invention provides a method of forming a gate dielectric layer of trench semiconductor device, the method includes the steps of forming a first trench in a silicon substrate, growing a thermal oxide layer on the sidewalls and bottom of the first trench, depositing a layer of nitride over the thermal oxide layer, etching away the thermal oxide layer and the nitride layer from the bottom of the first trench, forming a second trench at the bottom of the first trench to expose the silicon substrate on the sidewalls and bottom of the second trench, and depositing a selective oxide layer into the second trench over the silicon substrate to a desired thickness, wherein the desired thickness corresponds to a depth of the second trench and is greater than a thickness of the thermal oxide layer on the sidewalls of the trench.
In another embodiment, the invention provides a method of manufacturing a trench MOSFET. The method includes the steps of forming a plurality of trenches in a semiconductor substrate having a first conductivity type, each trench defined by sidewalls and a bottom; growing a thermal oxide on the sidewalls and the bottom of the trenches; etching away the thermal oxide layer on the sidewalls and the bottom of the trenches to expose portions of a surface of the semiconductor substrate; depositing a selective oxide layer on the bottom of the trenches over the exposed portions of the surface of the semiconductor substrate to a predetermined thickness, wherein the predetermined thickness is greater than a thickness of the thermal oxide layer on the sidewalls of the trenches; lining the oxide layer and selective oxide layer and filling the trenches with polysilicon; doping the polysilicon with a dopant having a first conductivity type; patterning the substrate and implanting a dopant having a second conductivity type to form a well into which the trenches are positioned; patterning the substrate and implanting a dopant having the second conductivity type to form a plurality of heavy bodies positioned within the well and between trenches; and patterning the substrate and implanting a dopant having the first conductivity type to form source regions within the well, the source regions positioned adjacent to and on opposite sides of each trench.
In yet another embodiment, the invention provides a method forming a trench MOSFET. The method includes the steps of forming a plurality of primary trenches in a semiconductor substrate, each primary trench having sidewalls and a bottom; forming a first dielectric layer on the sidewalls and the bottom of the primary trenches; forming a second dielectric layer over the first dielectric layer; etching through the first and second dielectric layers at the bottom of the primary trenches and into the semiconductor substrate to form a plurality of secondary trenches; filling the secondary trenches with an oxide to a predetermined depth; removing the first and second dielectric layers from the primary trench sidewalls; and forming a gate oxide layer on the primary trench sidewalls.
REFERENCES:
patent: 4914058 (1990-04-01), Blanchard
patent: 4941026 (1990-07-01), Temple
patent: 4967245 (1990-10-01), Cogan et al.
patent: 4992390 (1991-02-01), Chang
patent: 5164325 (1992-11-01), Cogan et al.
patent: 5298781 (1994-03-01), Cogan et al.
patent: 5473176 (1995-12-01), Kakumoto
patent: 5770878 (1998-06-01), Beasom
patent: 5801417 (1998-09-01), Tsang et al.
patent: 5879994 (1999-03-01), Kwan et al.
patent: 6198127 (2001-03-01), Kocon
patent: 6265269 (2001-07-01), Chen et al.
Technical Literature from Applied Materials, Farhad Moghadam, “Delivering Value Around New Industry Paradigms,” pp. 1-11, vol. 2, Issue, Nov. 1999.
Technical Literature from Quester Technology, Model APT-4300 300mm Atmospheric TEOS/Ozone CVD System, No date.
Technical Literature from Quester Technology, Model APT-6000 Atmospheric TEOS-Ozone CVD System, No date.
Technical Literature from Semiconductor Fabtech, Curtis, et al., APCVD TEOS: 03 Advanced Trench Isolation Applications, 9th Edition, No date.
Technical Literature from Semiconductor International, John Baliga, Options for CVD of Dielectrics Include Low-k Materials, Jun. 1998.
Technical Literature from Silicon Valley Group Thermal Systems, APNext, High Throughout APCVD Cluster Tool for 200 mm/300 mm Wafer Processing, No date.
LandOfFree
Selective oxide deposition in the bottom of a trench does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Selective oxide deposition in the bottom of a trench, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Selective oxide deposition in the bottom of a trench will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2850538