Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-18
2002-09-17
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S435000
Reexamination Certificate
active
06451654
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating a self-aligned split gate flash memory, and more particularly to a process for fabricating a self-aligned split gate flash memory, involving formation of a nitride liner layer and an insulating spacer in the trench to avoid current leakage and form a sharper polysilicon tip.
2. Description of the Prior Art
Flash memory is a type of erasable programmable read-only memory (EPROM), which in turn is a type of non-volatile memory. In general, flash memory includes two gates. One of the gates, known as a floating gate, is used for charge storage. The second gate, known as a control gate, is used for controlling the input and output of data. The floating gate is located beneath the control gate, and is generally in a floating state because there is no connection with external circuits. The control gate is normally wired to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Therefore, in recent years, flash memory has been widely utilized in electrical consumer products, such as digital cameras, digital video cameras, cellular phones, laptop computers, mobile cassette players, and personal digital assistants (PDA).
The conventional process for fabricating flash memory usually uses photomasks to define the devices. Since the precision of the photomasks is limited, misalignment usually occurs for devices with a smaller line width. This causes open circuits or short circuits, and the electrical properties of the flash memory fail. Therefore, the device size of the conventional flash memory is limited by the design rule, so it is difficult to shrink the device size.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the above-mentioned problems and provide a process for fabricating a split gate flash memory in a self-aligned manner, which decreases tolerance and shrinks the device size.
Another object of the present invention is to provide a process for fabricating a split gate flash memory to avoid current leakage.
A further object of the present invention is to provide a process for fabricating a split gate flash memory to form a sharper polysilicon tip, which is helpful in erase operations.
To achieve the above objects, according to a first aspect of the present invention, the process for fabricating a self-aligned split gate flash memory includes successively forming a gate oxide layer, a first polysilicon layer, and a first mask layer on a semiconductor substrate; patterning the gate oxide layer, first polysilicon layer, and first mask layer; forming a first insulating spacer on the sidewalls of the patterned gate oxide layer, the first patterned polysilicon layer, and the first patterned mask layer; forming a trench in the substrate using the first patterned mask layer and the first insulating spacer as a mask; filling an insulator into the trench; removing the first patterned mask layer and a part of the first insulating spacer to expose the first patterned polysilicon layer; forming a second patterned mask layer on the first patterned polysilicon layer while exposing a part of the first polysilicon layer to define a floating gate region; selectively oxidizing the exposed surface of the first polysilicon layer using the second patterned mask layer as a mask to form a polysilicon oxide layer; removing the second patterned mask layer; using the polysilicon oxide layer as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate; and successively forming an intergate insulating layer and a second patterned polysilicon layer as a control gate on the polysilicon oxide layer.
According to a second aspect of the present invention, the process for fabricating a self-aligned split gate flash memory includes successively forming a gate oxide layer, a first polysilicon layer, and a first mask layer on a semiconductor substrate; patterning the gate oxide layer, first polysilicon layer, and first mask layer; forming a trench in the substrate using the first patterned mask layer as a mask; filling an insulator into the trench such that the height of the insulator is lower than the height of the first patterned mask layer to form a recess in the trench; removing the first patterned mask layer to expose the first patterned polysilicon layer; forming a second patterned mask layer on the first patterned polysilicon layer while exposing a part of the first polysilicon layer to define a floating gate region, such that a part of the second mask layer remains on the sidewall of the first polysilicon layer in the recess to form a first insulating spacer; selectively oxidizing the exposed surface of the first polysilicon layer using the second patterned mask layer as a mask to form a polysilicon oxide layer; removing the second patterned mask layer; using the polysilicon oxide layer as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate; and successively forming an intergate insulating layer and a second patterned polysilicon layer as a control gate on the polysilicon oxide layer.
According to a third aspect of the present invention, the process for fabricating a self-aligned split gate flash memory includes successively forming a gate oxide layer, a first polysilicon layer, and a first mask layer on a semiconductor substrate; patterning the gate oxide layer, first polysilicon layer, and first mask layer; forming a first insulating spacer on the sidewalls of the patterned gate oxide layer, the first patterned polysilicon layer, and the first patterned mask layer; forming a trench in the substrate using the first patterned mask layer and the first insulating spacer as a mask; filling an insulator into the trench such that the height of the insulator is lower than the height of the first patterned mask layer to form a recess in the trench; removing the first patterned mask layer and a part of the first insulating spacer to expose the first patterned polysilicon layer; forming a second patterned mask layer on the first patterned polysilicon layer while exposing a part of the first polysilicon layer to define a floating gate region, such that a part of the second mask layer remains on the sidewall of the first polysilicon layer in the recess to form a second insulating spacer; selectively oxidizing the exposed surface of the first polysilicon layer using the second patterned mask layer as a mask to form a polysilicon oxide layer; removing the second patterned mask layer; using the polysilicon oxide layer as a mask to remove the underlying first polysilicon layer in a self-aligned manner to form a floating gate; and successively forming an intergate insulating layer and a second patterned polysilicon layer as a control gate on the polysilicon oxide layer.
By means of selectively oxidizing the surface of the first polysilicon layer to form a polysilicon oxide layer, the floating gate can be formed in a self-aligned manner. Thus, the device size can be shrunk.
During the oxidation process to form the above polysilicon oxide layer, the nitride liner layer and the insulating spacer formed in the trench and the insulating spacer formed in the recess above the trench insulator can prevent oxygen entering from the side. Thus, a sharper polysilicon tip can be formed, which is helpful in erasing operation. Also, this can prevent the line width of floating gate from size reduction and avoid current leakage.
REFERENCES:
patent: 6140182 (2000-10-01), Chen
patent: 6159801 (2000-12-01), Hsieh et al.
patent: 6309928 (2001-10-01), Sung et al.
patent: 6358769 (2002-03-01), Lin et al.
patent: 11-103033 (1999-04-01), None
Huang Chung-Lin
Huang Yung-Meng
Lin Chi-Hui
Chaudhari Chandra
Nanya Technology Corporation
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