Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-08-23
2002-03-12
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080
Reexamination Certificate
active
06356487
ABSTRACT:
TECHNICAL FIELD
This invention relates to memory devices, and, more particularly, to a dual mode flip-flop that may be used in the data path of a memory device that is optimized to either normal operation or to compressed data testing.
BACKGROUND OF THE INVENTION
Memory devices, such as static random access memories (“SRAMs”) and dynamic random access memories (“DRAMs”), each include one or more arrays of memory cells adapted to store data. The data are normally coupled to and from the memory array, and to each memory cell in the array, in complimentary form. Data are thus coupled to or from the array through an I/O line, and its compliment I/O*. For a read memory access, output data are coupled from the array through the complimentary I/O lines to a flip-flop. The flip-flop may be coupled to one of several pairs of I/O lines using a multiplexer or other switching circuitry. The flip-flop stores the output data and applies the data to an output data buffer that, in turn, couples the data to an externally accessible data bus terminal. Again, using a multiplexer or other switching circuitry, each of several flip-flops may be alternatively coupled to the data buffer.
In the past, flip-flops used as described above provided a complimentary output that was coupled to the data buffer through complimentary data lines extending from the flip-flop to the data buffer. However, these data lines must often be fairly long because of the considerable distance between the flip-flop, which is often positioned near an array, and the data buffer, which may be positioned some distance away near the periphery of a semiconductor die on which the memory device is formed. Since the value of the data can be determined from the logic level on either one of the two complimentary data lines, one of the complimentary data lines is essentially superfluous. As a result, memory devices have more recently used a single data line to couple output data from the flip flop to the data buffer. These “single-ended” data lines are used with a flip-flop having a single-ended output terminal. In contrast, “double-ended” data lines are coupled to flip-flops that provide a complimentary pair of double-ended outputs. A single-ended data path can save a significant amount of area on the surface of the semiconductor die and thus help reduce the cost of memory devices.
Although single-ended data paths can provide more efficient use of the semiconductor die surface, they are not as well suited for compressed data testing of memory devices. As is well known in the art, compressed data testing is commonly used to efficiently test memory devices during production and use. Flip-flops providing a double-ended output, which are used in a double-ended data path, are more suitable for compressed data testing. Flip-flops providing a single-ended output, which are used in single-ended data paths, require more expensive circuitry for providing the proper signals and routing them to appropriate circuitry for compressed data testing.
In the past, designers of memory devices had a choice of using either a single-ended data path to more efficiently use the surface area of the semiconductor substrate or using a double-ended data path to facilitate compressed data testing. This compromise left the resulting memory devices with either a relatively large cost or relatively little testing capability. However, it would be desirable to provide memory devices having the cost efficiencies of a single ended-data path and the compressed data testing capabilities of a double-ended data path.
SUMMARY OF THE INVENTION
A flip-flop used in the read data path of a memory device receives and latches data from a memory array. In a normal operating mode, single-ended data are coupled from the flip-flop to a data output buffer. In a test mode, double-ended data are coupled from the flip-flop to a compression circuit. The compression circuit compares the data from the flip-flop to data from another flip-flop, and outputs corresponding test data to the data output buffer. The flip-flop thus operates in either of two modes, namely a single-ended output mode or a double-ended output mode.
REFERENCES:
patent: 5426612 (1995-06-01), Ichige et al.
patent: 5659508 (1997-08-01), Lamphier et al.
Hoang Huan
Le Thong
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