Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1998-12-31
2002-03-19
DeCady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06360344
ABSTRACT:
FIELD OF THE INVENTION
The field of the present invention pertains to built in self testing of memory integrated circuits. More particularly, the present invention pertains to a method and system for an efficient built in test of the addressing circuits of a memory integrated circuit to detect cross port faults, bit shorts, and address mismatch faults, and the like.
BACKGROUND OF THE INVENTION
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society's reliance on such systems is likewise increasing, making it critical that the systems obey the properties their designers intended. Typically, the more powerful and complex the system, the greater its utility and usefulness. However, as these computer and software implemented systems and processes become more powerful, detecting and correcting flaws within the systems becomes increasingly difficult.
As integrated circuits, and particularly memory integrated circuits, have become more complex and more dense, they have become progressively harder to test in order to ensure correct and complete functionality. For example, with current technology, as memory size increases, the time which a memory integrated circuit (e.g., DRAM) emerging from a fabrication process line spends in testing increases as well. This increase incurs an additional cost on DRAM manufacturing.
DRAM devices are achieving greater and greater densities. Higher densities are achieved by reducing the amount of space between memory cells which comprise the DRAM integrated circuit. As such, the place and route tolerances for the integrate circuit are reduced, and the potential for introducing errors and introducing structural faults in the circuit itself increases.
The testing cost can be very significant for the latest and largest high density DRAM integrated circuits. This is particularly true in the case of multiport memory integrated circuits, and especially so with multiport memories embedded within logic chips. High density, embedded multiport memory integrated circuits are among the more expensive integrated circuits to produce. Additionally, the nature of the faults encountered in such high density integrated circuits requires the use of sophisticated algorithms in order to ensure adequate error detection. The complicated placement of the internal structure of high density integrated circuits also greatly increases the difficulty detecting the above types of faults.
For example, and the case of a high density multiport memory device, the highly complex internal structure of the integrate circuit, e.g., the complex place and route structure, increases the likelihood of the introduction of cross port faults, bit storage faults, and address mismatch type faults. Testing of these types of memory devices require simultaneous access of the memory cells of the device in a specific pattern, across specific ports. The intricacies of the pattern used in accessing memory cells to implement testing routines is largely determined through analysis of the place and route information used in fabricating the memory device. Using such information, specialized algorithms access the memory cells in a specific pattern, in accordance with the place and route information for the particular types of devices, to determine whether structural faults between the closely spaced memory cells (e.g., such as a bit short, or the like) exist.
High density multiport memories are becoming more common among computer systems. This is especially true in the field of telecommunications applications. The incorporation of multiple access ports provides greater flexibility in the design of applications which require large amounts of storage. Multiple access ports in memory devices provide new opportunities for system designers to add functionality and flexibility to computer system designs. An unfortunate drawback, however, is the fact that such multiport designs increased complexity of the internal wiring of the memory devices (e.g., the place and route structure). As described above, closely packed memory cells and closely packed wiring access increases the occurrence of certain types of faults. These faults are briefly described below.
One type of faults is referred to as “cross port” decoder faults. These are faults between the decoder of two ports of a memory integrated circuit device. Another type of fault is referred to as “bit short” faults. These are faults between bit lines of two ports. “Address mismatch faults” are due to non-identical mapping of logical addresses to physical memory cells on two ports of a multiport memory integrated circuit device.
Other types of faults include “contention logic” faults, which referred to faults in the circuits inside a memory device that arbitrates simultaneous request write requests on the same memory cells. “Complex Coupling” faults are the faults which can occur due to simultaneous access of different memory cells through different ports that can disturb the contents of one or more neighboring memory cells (e.g., these faults can be both static and dynamic).
The emergence of high density multiport memory devices and logic type integrated circuits which include one or more embedded multiport memories thus require new methods and new systems for testing the devices as they emerge from fabrication. Past testing techniques are proving inadequate. For example, complex coupling faults do not exist in single port type memory devices, and hence, the vast majority of prior art algorithms designed to test for the presence of single port faults are not even applicable for testing for complex coupling faults, let alone being able to reliably detect them.
Technology for testing multiport memories has not been thoroughly developed in the current prior art. One prior art technique addressed testing multiport memories by accessing the memory ports through external connections. The problem with this approach is that external access to the address ports cannot be assumed to always be available (e.g., as is the case where an embedded memory has no direct access from chip I/O pins to its ports). Another past technique involves the use of serial type algorithms, wherein single port memory type tests are repeated for each port, for the case of embedded dual port memories.
Another prior art technique for testing shorts between bit and word lines involves the use of special shadow write operations designed to meet the requirement of activating same two cells in the same physical columns. This assumes the knowledge of the physical placement of the rows and columns of the integrate circuit (e.g., the place and route structure), which may not always be available to the designer. Yet another prior art technique introduced a new coupling fault model called “complex coupling” in the dual-port memories which takes into account effect on a third cell of simultaneous accesses in two other cells. The problem with a solution is that it also assumes some topological restrictions and knowledge of physical placement of cells in the memory.
Yet another prior art technique proposes another fault model to account for the effects of simultaneous access of multiple cells in the neighborhood onto the base cells. This technique uses a “O(sqrt(N)” algorithm to test for these faults. This technique also assumes a specific placement of the cells in the memory and modifies the input to the decoders of the memory device to achieve this low complexity. This technique is capable of testing for the existence of cross-port decoder and address mismatch faults, however, knowledge of physical placement of cells in the memory device is required in order to detect these types of faults .
Thus, in summary, of the specific types of faults encountered in the design in fabrication of multiport memory devices, cross port faults and bit shorts are the only types usually addressed. To detect even these two types of faults, the above prior art techniques need to assume the knowledge of the physical placement of cells in the m
Ayres Timothy
Khoche Ajay
Chase Shelly A
DeCady Albert
Synopsys Inc.
Wagner , Murabito & Hao LLP
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