Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
1999-03-02
2002-05-21
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
C710S008000, C710S015000, C710S062000, C710S072000, C710S120000
Reexamination Certificate
active
06393498
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data-processing system and method using memory-remapping technique. Such invention is designed to reduce the workload of processors, such as central processing units (CPUs) in personal computers, and to serve the data transfer requirement of various peripheral devices.
2. Description of the Related Art
Memory is an infrastructure block in data-processing or computing systems (hereafter is referred to as “the System”). Under normal operation, the System must spend a lot of time to move data from and write data into the memory. Therefore, how to effectively access memory is a critical issue when assessing the System's overall performance.
FIG. 1
(Prior Art) is a block diagram which illustrates the fundamental structure of the System. As shown in
FIG. 1
, the System includes processor
1
, system controller
3
, memory
5
and several peripheral devices such as peripheral device
7
and peripheral device
9
. Processor
1
is the key component in the System for performing various data-processing operations, such as arithmetic and logical operations, and data transfer operations. Memory
5
, usually implemented by dynamic random access memories (hereafter referred as DRAMs), is a main storage device for storing major program codes and data. Peripheral devices
7
and
9
are used to communicate with the exterior or supplement extra functions to the System. Some popular peripheral devices, such as graphic cards, modems with I/O interface and Moving Picture Experts Group's cards (MPEG cards), are prevalent in most computing or data-processing systems. System controller
3
, which is installed between processor
1
, memory
5
and peripheral devices
7
and
9
, is used to link processor
1
and the peripheral devices. In addition, system controller
3
provides an accessing scheme for memory
5
to help processor
3
and the peripheral devices to access memory
5
. From the viewpoint of memory accessing, system controller
3
should handle all requests ready for accessing memory
5
in the predefined timing, from either processor
1
or peripheral devices
7
and
9
. It is noticed that some essential components in modern computer systems are omitted from the illustrated system architecture, such as caches in the memory hierarchy, shown in FIG.
1
.
FIG. 2
(Prior Art) illustrates detail structures of system controller
3
and memory
5
in the System. In the modern memory technology, physical memory devices, such as DRAMs, are usually divided into several memory banks that can be accessed independently. As shown in
FIG. 2
, memory
5
is consisted of memory bank
5
a,
memory bank
5
b,
memory bank
5
c,
and so on, which can be accessed independently under the control of dedicated access controlling signals (not shown). On the other hand,
FIG. 2
also illustrates three memory access components of system controller
3
, including access control circuit
31
, page management circuit
33
and open-page address table (stored in memories)
35
. Access control circuit
31
is responsible for receiving external access requests, which come from either processor
1
or other peripheral devices. It is also responsible for physically executing the access control protocol of memory
5
. Page management circuit
33
helps the access control circuit
31
in access controlling, especially in page management. Each page of memory
5
contains a fixed number of bytes that can be accessed in the faster operation mode. The byte number of each page depends on the practical application, usually about 32 bytes or more. If a page is “open”, it means that all memory locations contained in this page can be accessed (esp. the writing operation) faster than those contained in “Non open” pages since pre-fetch operations are not required. Open-page address table
35
, which is implemented by memory devices, is used to memorize the addressing information of all “open” pages in memory
5
. Generally speaking, page management circuit
33
can properly alter all the addressing information that is stored in open-page address table
35
according to the physical access operations of access control circuit
31
. On the other hand, page management circuit
33
also assists access control circuit
31
to effectively access to memory
3
, with reference to the addressing information of all open pages maintained in the open-page address table
35
.
In the system architecture shown in
FIG. 1
, processor
1
and other peripheral devices have to frequently access to the required storage locations of memory
5
to perform desired applications.
FIG. 3
(Prior Art) shows the schematic system diagram of such an access example, in which peripheral device
9
provides the System with specific data and then peripheral device
7
performs an operation on these specific data. The example illustrated in
FIG. 3
can be thought of as the case that a modem device (i.e., peripheral device
9
) downloads an archived video file from the Internet, such as one encoded by the MPEG scheme, and the System employs a dedicated MPEG card (i.e., peripheral device
7
) to decode or recover the video data. In general system architecture, each of the peripheral devices is assigned with a dedicated segment of memory used to communicating with each other. In
FIG. 3
, peripheral device
7
accesses memory segment B
2
by using addresses ADDR#
2
that are dedicated to peripheral device
7
; the peripheral device
9
accesses memory segment B
1
by addresses ADDR#
1
that are dedicated to peripheral device
9
.
In the conventional data-processing system, there are five steps required in this example, which are denoted as S
1
~S
5
, respectively. To demonstrate the whole process, these steps are sequentially described as follows. In step S
1
, peripheral device
9
stores data, which may be an archived file, to the memory segment B
1
mapping to the addresses ADDR#
1
. Next, processor
1
must move the inputted data stored in memory segment B
1
to memory segment B
2
mapping to the addresses ADDR#
2
that are dedicated to peripheral device
7
. Accordingly, processor
1
reads the data stored in memory segment B
1
(step S
2
) and writes the data to the memory segment B
2
(step S
3
). It is obvious that the workload of processor
1
increases since processor
1
must involve in the process of moving data. Finally, peripheral device
7
can retrieve the data currently stored in memory segment B
2
(step S
4
), perform the desired operation on these data, such as MPEG decoding, and then write the resulting data back to memory segment B
2
(step S
5
).
The drawback of conventional memory access mechanism is twofold. First, processor
1
must involve itself in the process of moving data between two memory segments that are individually assigned to two different peripheral devices. It means that the processor
1
must waste time to execute the required data transfer operations and delay other necessary tasks. Second, moving data from memory segment B
1
to memory segment B
2
is a time-consuming process. Accordingly, it is obvious that the overall system performance will be degraded due to the task of moving data between two memory segments in such an application.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method and system for facilitating data exchange between two isolated memory segments and reducing the workload and the processing time of the system processor, thereby increasing the overall performance of the System.
The present invention achieves this objective by providing an enhanced system controller that supports memory-remapping technology to the System. The memory device in the System contains a first memory segment (or first set of physical storage locations) and a second memory segment (or second sets of physical storage locations). The system controller is operated under two operating modes. In the first operating mode, also called a normal mode, the system controller maps a first set of add
Hou Chien-Tzu
Hsu Hsiu-Ying
Gaffin Jeffrey
Mai Rijue
Mentor ARC Inc.
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