Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-24
2002-01-08
Wilczewski, Mary (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S706000, C438S720000, C438S945000
Reexamination Certificate
active
06337238
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to semiconductor devices and more particularly to a random access memory having a ferroelectric film (FRAM; ferroelectric random access memory) or a miniaturized dynamic random access memory (DRAM) having a high permittivity dielectric film.
With recent advancements in memory technology, particularly with regard to the art of device miniaturization, DRAMs that use a high permittivity dielectric film for the memory cell capacitor are studied intensively. Further, intensive efforts are being made also for FRAMs that use a ferroelectric film for storage of information. An FRAM stores information in the ferroelectric film in the form of polarization and has advantageous features of a non-volatile nature of information storage and a large access speed.
Conventionally, DRAMs are formed to have a dielectric film of SiN or SiO
2
for the capacitor dielectric film of the memory cell capacitor. With an increase of the integration density and a corresponding miniaturization of the device, however, the use of such a conventional dielectric film has caused the problem of insufficient capacitance for the memory cell capacitor due to the excessive miniaturization of the memory cell capacitor. As a DRAM stores information in the memory cell capacitor in the form of electric charges, the decrease of the capacitance of the memory cell capacitor, which occurs inevitably as a result of the device miniaturization, causes a problem of an unreliable read/write operation or an unreliable holding of the stored information.
In order to compensate for such a decrease of the memory cell capacitance, it is proposed to use a high-permittivity dielectric film for the memory cell capacitor of a DRAM. For example, the use of a double oxide film such as (Ba, Sr)TiO
3
(called hereinafter BST) or SrTiO
3
(called hereinafter STO) is studied intensively for this purpose.
Further, it should be noted that a double oxide is used also in FRAMs for a capacitor dielectric film, wherein the double oxide used in a FRAM is a ferroelectric material that shows a spontaneous polarization below a Curie temperature. For example, the use of Pb(Zn, Ti)O
3
(called hereinafter PZT) is studied intensively for the dielectric film of an FRAM.
As these dielectric or ferroelectric films of double oxides have a substantially different nature as compared with a silicon nitride (SiN) film or a silicon oxide (SiO
2
) film used conventionally for the capacitor dielectric film of a DRAM, there arises various difficulties when the semiconductor memory device is fabricated to have a conventional structure.
FIG. 1
shows an example of the memory cell of a conventional FRAM that uses a ferroelectric film for the capacitor dielectric film, wherein it should be noted that
FIG. 1
shows only the essential part of the device including a local interconnection pattern, while the illustration of interlayer insulation films and interconnection patterns provided further thereon is omitted for the sake of simplicity.
Referring to
FIG. 1
, the FRAM is constructed on a Si substrate
101
carrying a field oxide film
102
, wherein the field oxide film
102
defines a memory cell region on the substrate
101
as usual. Further, the Si substrate
101
carries thereon a gate electrode
104
extending across the memory cell region, wherein a gate insulation film
103
is interposed between the substrate
101
and the gate electrode
104
in the foregoing memory cell region. Further, diffusion regions
105
and
106
are formed at both sides of the gate electrode
104
in the memory cell region as a source and a drain of the memory cell transistor.
The gate electrode
104
, on the other hand, is covered by a first interlayer insulation film
107
, and a bit line
108
is provided on the interlayer insulation film
107
in electrical contact with the diffusion region
105
via a contact hole formed in the interlayer insulation film
107
. The bit line
108
is then covered by a second interlayer insulation film
109
, on which a memory cell capacitor is formed.
As indicated in
FIG. 1
, the memory cell capacitor includes a lower capacitor electrode
110
provided directly on the interlayer insulation film
109
, and a capacitor dielectric film
111
is provided on the lower capacitor electrode
110
. Further, an upper capacitor electrode is provided on the capacitor dielectric film
111
so as to sandwich the capacitor dielectric film
111
between the lower and upper capacitor electrodes
110
and
112
. A third interlayer insulation film
113
further covers the memory cell capacitor thus formed on the second interlayer insulation film
109
.
The structure thus formed is provided with a via-hole extending through the interlayer insulation films
107
,
109
and
113
, and a local interconnection pattern
114
is provided on the interlayer insulation film
113
in electrical contact with the diffusion region
106
exposed by the via-hole and further in electrical contact with the upper capacitor electrode
112
, such that the local interconnection pattern
114
connects the diffusion region
106
to the upper capacitor electrode
112
of the memory cell capacitor.
The fabrication of the FRAM of
FIG. 1
may be carried out as follows.
First, the Si substrate
101
is formed with the field oxide film
102
such that the field oxide film
102
defines the memory cell region on the substrate
101
. Further, a MOS transistor having the gate electrode
104
is formed in the memory cell region as the memory cell transistor of the FRAM, wherein the gate electrode
104
is insulated from the substrate
101
by the gate insulation film
103
and the MOS transistor further includes the diffusion regions
105
and
106
at both sides of the gate electrode
104
.
Next, a silicon oxide film is deposited on the structure thus obtained including the gate electrode
104
as the first interlayer insulation film
107
, and a contact hole is formed in the interlayer insulation film
107
so as to expose the diffusion region
105
by a well known photolithographic process After the contact hole is thus formed, a layer of WSi is deposited on the interlayer insulation film
107
including the contact hole such that the WSi layer contacts the exposed diffusion region
105
at the contact hole. By patterning the WSi layer thus formed subsequently, the bit line
108
is obtained.
Next, another silicon oxide film is deposited on the structure thus obtained, to form the second interlayer insulation film
109
, and the formation of the lower capacitor electrode
110
is made further on the insulation film
109
, wherein the formation of the lower capacitor electrode
110
is made by depositing a Ti film and a Pt film consecutively to form a Pt/Ti structure.
The Pt/Ti film thus formed is then patterned by an ion milling process by using a resist mask to form the lower capacitor electrode
110
, and a PZT film is deposited further on the lower capacitor electrode
110
by an RF sputtering process, for example. The PZT film thus deposited is patterned by an ion milling process by using the resist mask to form the capacitor dielectric film
111
. Further, a Pt film is deposited on the dielectric film
111
, followed by an ion milling process to form the upper capacitor electrode
112
, similarly to the lower capacitor electrode
110
. Thereby, the memory cell capacitor is formed on the interlayer insulation film
109
.
After the memory cell capacitor is formed as such, a silicon oxide film is deposited on the interlayer insulation film
109
as the third interlayer insulation film
113
so as to cover the memory cell capacitor and the diffusion region
106
is exposed by forming the via-hole noted before, such that the via-hole extends through the interlayer insulation films
107
,
109
and
113
. Further, a contact hole is formed in the interlayer insulation film
113
to expose the upper capacitor electrode
112
, and a conductor layer is deposited on the interlayer insulation film
113
so as to establish an electrical
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Thomas Toniae M.
Wilczewski Mary
LandOfFree
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