Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2001-07-13
2002-09-24
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S911000
Reexamination Certificate
active
06455440
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for preventing stringers in memory devices, and more particularly to a method for preventing polysilicon stringers in memory devices with flat cells by forming a floating gate structure with multi-level oxidation rates.
2. Description of the Prior Art
A memory device for storing data has a great significance in a data processing system. Memory devices, such as random access memory (RAM), read-only memory (ROM), and the like, are known in the art. Non-volatile memory devices, and particularly so-called “flash” memory devices, have become increasingly more popular in data storage applications. Generally, an array of flash memory cells may be formed on a semiconductor substrate in a series of rows and columns, accessed by conductors referred to as word lines and bit lines.
FIG. 1
illustrates a top view of a portion of an array
10
.
FIG. 2
is a cross-sectional view taken along a cutting line
2
—
2
in FIG.
1
. Typically, the layout of a flash memory array is shown as
FIG. 1
, and the cross-sectional structure of a flash memory cell is depicted in FIG.
2
.
Referring to FIG.
1
and
FIG. 2
, each memory cell
100
is formed in the semiconductor substrate
101
by, for example, formation of source
110
and drain
112
regions with a channel region position between the drain
112
and source
110
regions. A tunnel oxide layer
114
or gate dielectric layer (not shown in
FIG. 1
) is formed on the substrate
101
separating a first polysilicon layer or floating gate layer
116
from the source
110
and drain
112
regions. The control gates of the respective cells that are formed in a lateral row share a common word line (WL)
120
associated with the row of cells. That is to say, a second polysilicon layer or control gate layer
120
is formed over the floating gate layer
116
separated by an interpoly dielectric layer
118
(not shown in
FIG. 1
) such as oxide-nitride-oxide (ONO) sandwich. Field oxide regions
102
separate and isolate adjacent memory devices along a word line
120
. Additionally, for the purpose of improving the coupling ratio, an extra polysilicon layer
124
is formed between the floating gate layer
116
and the interpoly dielectric layer
118
to enhance the surface area of the floating gate, wherein adjacent floating gate layers
116
is isolated by a dielectric layer
122
, as shown in FIG.
3
A.
FIG. 3A
is a cross-sectional view of a cell with enhanced floating gate structure similar to that taken along a cutting line
3
—
3
in FIG.
1
. That is an extra polysilicon layer is formed on the floating gate layer in the process of forming a memory cell similar to that in
FIG. 1. A
first polysilicon layer
116
(first floating gate layer) in strip shape is formed between two field oxide regions over the semiconductor substrate
101
with the tunnel oxide layer
114
in between. For the reason of simplicity, the field oxide region is not shown. Then, an oxidation process is performed, such that adjacent first polysilicon strip
116
is isolated by a dielectric layer
122
. A second polysilicon layer
124
(second floating gate layer) is formed on the first polysilicon layer
116
. Then, the interpoly dielectric layer
118
and the control gate layer
120
are formed to accomplish the memory cell. It is well known that a perfect vertical profile control is very difficult to accomplish in the fabrication of semiconductor devices, especially after numbers of oxidation processes have applied. That is in an oxidation process, the portion of polysilicon layer which is close to the surface is usually oxidized faster than the portion that is far from the surface. Thus, due to the anisotropic etch process of the first floating gate layer
116
does not provide ideally anisotropic profile, the vertical profile of the first floating gate strip
116
is only controlled close to ideally formed. Moreover, after the oxidation process of forming the dielectric layer
122
and the interpoly dielectric layer
118
such as ONO layer, the floating gate layer
116
with sloped sidewalls can not be ignored. During the processing of an array with layout similar to that shown in
FIG. 1
, a problem occurs involving polysilicon stringers due to complex oxidation processes and the non-ideal vertical profile control. If the vertical profile of a floating gate layer is imperfect, when delineating memory cells along a given word line, polysilicon stringers results from anisotropic etching of the floating gate layer. The non-ideal vertical profile causes the reduction of the process tolerance resulting in reliability problem, in other words, resulting in the yield lost.
When portions of the control gate layer
120
is anisotropically etched to define the various word lines for the memory device, portions of floating gate layer between two adjacent word lines (about the source region
110
shown in
FIG. 1
) is also anisotropically etched away preventing adjacent word lines short together. However, it is well known that anisotropic etch do not repeatedly provide ideally anisotropic profiles, especially the application of oxidation processes makes the control for anisotropic profile of the floating gate layer
116
with sloped sidewalls becoming more difficult. A non-ideal anisotropic etch profile results in remnants of floating gate layer, which are the polysilicon stringers
126
, as shown in FIG.
3
B. That is to say, when the floating gate layer
116
is sequentially etched, the sloped sidewalls of the floating gate layer
116
is shielded by the dielectric layer
122
resulting in polysilicon stringers
126
. As illustrated in
FIG. 4
, a perspective view of bottom portion of etched region between two word lines is shown. It is clear that the polysilicon stringers
126
pose a substantial reliability problem since the polysilicon stringers
126
in the etched region can short out the word lines in regions
128
and
130
, respectively. That is, instead of the etched region electrically isolating the word lines in regions
128
and
130
from one another, the polysilicon stringers
126
span the etched region shielded by the dielectric layer and cause the gates in the regions to be shorted together.
Recently, a floating gate layer of inverted triangle shape has been proposed. However, the etching process of forming an inverted triangle floating gate is more complicated and very difficult to control, and has difficulties in rework through proper in-line monitor process. When the inverted triangle floating gate technique is associated with the application of extra polysilicon floating gate, the formation of a dielectric layer between adjacent inverted triangle floating gates encounters another gap-filling problem. Therefore, there is a strong need to form memory devices without polysilicon stringers and thereby reduce reliability problems due to shorted word lines.
SUMMARY OF THE INVENTION
The present invention is directed toward a method for preventing polysilicon stringer in memory devices. The key aspect of the present invention is the application of a floating gate structure with multi-level oxidation rates the lower portion of the floating gate structure the higher oxidation rates, such as a floating gate structure with two polysilicon layers of different doping concentration or crystallinity the lower polysilicon layer the higher doping concentration, or the lower polysilicon layer the higher crystallinity. Therefore, in a later oxidation process a desired profile of the polysilicon floating gate structure for etching process is formed, that is from lower portion to higher portion of the floating gate structure an increasing width profile is formed. The width of the upper portion of the floating gate structure is bigger than that of the lower portion of the floating gate structure. Thus, the anisotropic etching process of isolating the word lines maintains an ideal profile control, in other words, the polysilicon stringers in the etched region which short out the wo
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