Method to differentiate source/drain doping by using oxide...

Details Method to differentiate source/drain doping by using oxide... Method to differentiate source/drain doping by using oxide...

2000-05-08

2002-03-26

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S525000

Reexamination Certificate

active

06362061

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit manufacturing. More particularly, the present invention relates to reducing the steps in making Metal Oxide Semiconductor Field-Effect Transistor(hereinafter, MOSFET) source drain implants with extensions.
2. Discussion of the Related Art
Typically, a MOSFET circuit is fabricated from a single-crystal silicon substrate of a silicon wafer, which may be doped p-type or n-type. The significant steps in manufacturing a MOSFET circuit are described briefly in the following as background information. Initially, the surface of the silicon wafer is exposed to steam or dry oxygen at high temperature to form an oxide layer on the substrate. Subsequently, a layer of polycrystalline silicon (polysilicon hereafter) is deposited and patterned to form a gate structure. Thereafter, the source and the drain regions are formed by implanting dopants into the silicon substrate. However, if the source and the drain regions have extensions, and a different depth or doping levels are desired for such extensions, separate steps are required to form the source and drains and the extensions. However, high efficiency can be achieved if both the source and the drain regions and their respective extensions can be formed in one step using only one mask.
SUMMARY OF THE INVENTION
The present invention provides a method for manufacturing the source and the drain regions and their extensions in a single masking step. The method manufactures MOSFET devices in which the source and drain regions are associated with extension regions having depth and dopant levels different from those of the source and the drain regions.
A method of the present invention includes making a channel-shaped oxide structure surrounding the polysilicon gate. The oxide structure forms an implantation barrier for subsequent dopant implantation into the extension regions. Thus, when the source and drain regions are implanted at a given energy level, the extension regions are also implanted, but to a lower depth and a lower dopant concentration relative to the depth and dopant concentration of the source and the drain regions.


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The IEEE Standard Dictionary of Electrical and Electronics Terms, 6th ed, IEEE Std 100-1996, pp. 146.

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