Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-10-15
2002-04-23
Moise, Emmanuel L. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S034000, C714S039000, C714S733000, C714S734000, C712S043000, C712S227000
Reexamination Certificate
active
06378092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to the field of integrated circuit testing, and in particular, to test circuitry in an integrated circuit that controls the time within a clock cycle when a test sample is obtained.
2. Statement of the Problem
Integrated circuits are tested to find manufacturing defects and performance deficiencies. Testing is often performed using test circuitry within the integrated circuit. The test circuitry samples signals within the integrated circuit and provides these test samples to an external test system for analysis. Integrated circuit testing is described in I.E.E.E. standard 1149.1
Some test circuits scan the values in storage elements to provide the test samples. Unfortunately, the operation of the integrated circuit is stopped to perform the scan, and the scan destroys the value in the storage element. To get the integrated circuit back to the state just prior to the scan, the integrated circuit is reset and must operate as before until the point of interruption. Both the scan and the reset process take time. In addition, the scan only obtains the static value in the storage element, and does not indicate time-varying signal problems, such as late arrival or glitches.
Other test circuits use redundant storage elements that passively receive the outputs from operational storage elements. An example of such a test circuit is described in U.S. Pat. No. 5,530,706 which is hereby incorporated by reference into this application. Some of these test circuits use a clock to sample the output. Other test circuits use pulses at the edge of the clock cycle to sample the output. Unfortunately, the output is continually sampled at the same time relative to the clock cycle. The lack of dynamic control over the sampling time makes it difficult to identify time-varying signal problems, such as late arrival or glitches.
Some test circuits use a trigger circuit to initiate testing. An example of such a trigger circuit is described in U.S. Pat. No. 5,867,644 which is hereby incorporated by reference into this application. Unfortunately, these test systems also fail to dynamically control the sampling time within a clock pulse.
SUMMARY OF THE SOLUTION
The invention solves the above problems with test circuitry that samples a target signal at selected times within a clock cycle. The ability to select times within the clock cycle facilitates testing to characterize time varying problems, such as signal delays and glitches. Thus, the test circuitry provides for the advanced testing of integrated circuit speed and system inter-operation.
The integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuit. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.
In various embodiments of the invention, the selected time is a delay from a time point in the clock signal. The test circuitry generates a pulse after the delay and samples the target signal in response to the pulse. In various embodiments of the invention, the test circuitry samples the target signal in response to a trigger. The test circuitry compares internal signals from the integrated circuitry to a trigger condition and generates a trigger signal if the internal signals match the trigger condition.
REFERENCES:
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5530706 (1996-06-01), Josephson et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5644609 (1997-07-01), Bockhaus et al.
patent: 5867644 (1999-02-01), Ranson et al.
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