Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-23
2002-03-26
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S527000, C438S546000
Reexamination Certificate
active
06362056
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a method of making an alternative to dual gate oxide for high voltage operation and more particularly to a method of forming depleted conductor regions on a substrate for memory devices. This method is also applicable to memory technologies employing an insulating cap over gate conductor for forming border-less contact.
BACKGROUND OF THE INVENTION
Various techniques have been employed for forming high and low voltage devices on the same substrate. For example, U.S. Pat. No. 5,834,352 is directed to a method for making integrated circuits containing high and low voltage insulated-gate field effect transistors on the same substrate using different gate oxide thickness.
For forming depletion devices by doping a depletion layer into the channel region below the gate, U.S. Pat. No. 5,786,619 discloses a method of making depletion mode power metal oxide semiconductor field effect transistors (MOSFET) having a refractory gate electrode, wherein the base regions are formed by introducing into the layer dopant of one conductivity type. In particular, U.S. Pat. No. 4,472,871 describes a method of making a plurality of MOSFETs having different threshold voltages by the repeated steps of masking and implanting various ion implantation doses in channels.
In U.S. Pat. Nos. 5,770,494 and 4,782,033, there are disclosed processes for doping gates of metal oxide semiconductor devices through diffusion from a refractory layer. Further, U.S. Pat. No. 5,218,221 discloses threshold voltage adjustment by implanting into the channel region impurity ions at a tilt angle with a semiconductor substrate rotated, using the transfer gate electrode as a mask. CMOS devices in which the gates of the NMOS devices are doped n-type and the gates of the PMOS devices are doped p-type are disclosed in U.S. Pat. Nos. 5,010,032 and 4,555,842.
The conventional method comprises the step of doping polysilicon gates of both types of devices in which the doping level of the high voltage devices is less than that of the low to voltage devices such that the high voltage depletes the channel. For example, U.S. Pat. No. 5,637,903 is directed to a process for fabricating metal oxide semiconductor field effect transistors using one gate oxide thickness and resulting in both low and high operating voltage devices. The fabrication sequence has been developed to form an undoped or partially doped structure for high voltages and a doped structure for low voltages.
Further, U.S. Pat. No. 5,468,666 describes using a change in doping of polygate to permit placing both high and low voltage transistors on the same chip. High voltage transistor comprises a polysilicon gate doped at a low dopant level and low voltage transistor comprises a polysilicon gate doped at a high dopant level.
However, none of the conventional techniques describe a method of making an alternative to dual gate oxide for word line operation by forming doped and depleted conductor regions on a substrate, in which the doped low voltage devices are used for support devices and the depleted high voltage devices are used for word line devices.
In DRAM Technology CMOS support circuitry logic voltages do not scale with the array word line boost voltage requirements. In order to write the DRAM cell capacitor in a reasonable amount of time, a typical voltage level equal to Vdd+1 volt is applied to the word line, i.e., gate electrode of the transfer device, to increase the current drive of the transistor. When the DRAM transistor is in an off condition i.e., the gate is typically grounded, the requirement of the transfer device changes from writing to the cell to having it remain charged and not leak through the transfer device for as long a time as possible. In this case, the back gate voltage or body bias is typically set to a value between −0.5 volts and −1.0 volts, which inhibits cell leakage. Unfortunately this voltage level is also present during the write described above. This has the natural tendency of slowing the device down.
The conditions described above diametrically oppose each other with respect to the electric fields and device design. For example, in a typical 2.1 volt technology, e.g., 256 mB synchronous DRAM with 0.15 um lithography, the dielectric thickness (Tox) in the transistor support region is scaled to 4.5 nm. With this value of Tox, the maximum gate to drain field [Vg−Vd]/Tox is approximately 4.7MV/cm, the device design has a nominal logic support threshold voltage (Vt) of approximately 0.5 volts and thus the overdrive voltage equal to 1.6 volts (Vg−Vt). However, the DRAM transistor has a nominal threshold voltage of approximately 1.07 volts with the body voltage equal to −1 volts, and the oxide thickness equal to 6.2 nm, thus having an overdrive of 1.03 volts, if no wordline boost is employed.
Since current drive is roughly proportional to the overdrive squared, it becomes obvious under identical conditions that the drive of the DRAM device is 41% of the logic drive. In reality the situation is degraded further by the change in gate oxide thickness and other unique DRAM features that are not pertinent to this discussion. To overcome this deficiency, the DRAM array is compensated by increasing the word line voltage to Vdd +1V. This example results in an overdrive voltage equal to 2.03 volts, and a maximum gate to drain field of approximately 5MV/cm, which is typically the highest use field allowed.
The DRAM dual oxide process, i.e., logic support device/array transfer device are used for the first time in this 256 MB generation. Listed below in Table 1 is a cross section of recent DRAM power supply and field configurations. As can be observed, the system power supply (Vdd) does not scale directly with the oxide thickness, as is also the case with threshold voltage, and thus arises the need for reducing the field in the DRAM array. Unfortunately thickening the gate oxide is in a direct conflict with device scaling. For example the short channel effect, otherwise known as drain induced barrier lowering is adversely affected by thickening the gate oxide. This affect is electrically manifested as a reduction in threshold voltage for thick oxide as compared to thin oxide for otherwise equivalent device designs (i.e. same gate length and Vdd). This is shown in
FIG. 1
, where the thin and thick oxide devices are designed for the same long channel threshold voltage (Vth3), but the thin oxide device has a larger threshold voltage (Vth2) than does the thick oxide (Vth1) at the lithographically designed channel length (Leff). This drop in short channel Vt for the thick oxide device is due to enhanced drain-induced barrier lowering (DIBL). The threshold voltage measurement is shown for source to substrate potential at ground, and the drain at Vdd.
TABLE 1
DRAM Generation/Power Supply
Tox Logic -
Tox Array/
Product Type
Vdd
Max E field
Max E Field
64M EDO
2.8 Volts
8.0 nm - 3.5 MV/cm
8.0 nm - 4.9 MV/cm
64M Synch
2.5 Volts
7.5 nm - 3.3 MV/cm
7.5 nm - 4.7 MV/cm
256M Synch
2.1 Volts
4.5 nm - 4.7 MV/cm
6.2 nm - 5.0 MV/cm
The thick gate oxide in the array also degrades the sub-threshold slope, S, increasing adversely the off current in the device, which places an additional demand on the level of body bias required to suppress off-state leakage. The increased body bias adversely affects junction leakage, and places an upper bound on the usable body voltage range.
This is illustrated in
FIG. 2
where the gate voltage is swept for a constant drain and substrate voltage. Comparing the thin (solid line) to thick (dashed line) output characteristics, the sub-threshold slope S2 (thick) is greater than S1 (thin), thus the leakage current at Vgs=0 is greater for the thick device. In order to suppress the thick oxide leakage the magnitude of the body bias (Vbb) is greater for the thick oxide versus the thin oxide. (i.e., Vbb2>Vbb1). In reality higher Vbb may limit the useful Vbb voltage as united by the junction leakage of FIG.
2
.
Assuming a safe operational f
Mandelman Jack A.
Tonti William R.
Chaudhari Chandra
Huynh Yennhu B.
Rosenman & Colin, LLP.
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