Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2000-03-30
2002-04-16
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S257000, C438S258000, C438S259000, 43
Reexamination Certificate
active
06372564
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89105151, filed March 21, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing semiconductor device. More particularly, the present invention relates to a method of forming V-shaped flash memory such that level of integration for the memory is increased.
2. Description of Related Art
Conventional non-volatile memory can be divided into several types including erasable programmable read only memory (EPROM), electrical erasable programmable read only memory (EEPROM) and flash memory. Because input data are retained when power is turned off, they are ideal storage media for operational programs.
In general, a flash memory unit includes a floating gate for storing electric charges and a control gate for controlling the access of data. The floating gate is formed in the space within the control gate. The floating gate is normally in a floating state because the gate is not connected to any external circuit. On the other hand, the control gate is electrically connected to a word line and the drain terminal of a flash memory unit is electrically connected to a bit line.
To program data into a flash memory unit, electrons are injected into the floating gate unit near the drain terminal through a channel hot electron injection (CHEI). To erase data from a flash memory unit, electrons in the floating gate are channeled away via a source terminal through Fowler-Nordheim (FN) tunneling. For a flash memory unit having a conventional N-type ETOX structure, injection probability in a CHEI operation is only about 10
−9
. Hence, a higher voltage must be applied resulting in greater energy consumption and lower programming efficiency.
In addition, due to an increase in the level of integration, dimensions of each device in a silicon chip will decrease according to the design rules. Consequently, operating voltage of a device is also lowered correspondingly. Since a large coupling between the floating gate and the control gate will lower the voltage needed to operate a memory transistor, it is beneficial to increase the capacitance between a floating gate and a control gate.
There are three methods of increasing capacitor coupling between a floating gate and a control gate. They includes increasing the overlapping area between the floating gate and the control gate, decreasing the thickness of dielectric layer between the floating gate and the control gate and increasing the dielectric constant k of the dielectric layer. However, the dielectric layer between the floating gate and the control gate must have sufficient thickness to prevent trapped electrons in the floating gate from jumping into the control gate leading to device failure. On the other hand, increasing dielectric constant of the dielectric layer is not a simple task because it involves materials and techniques that are closely related to processing equipment.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a V-shaped flash memory structure capable of increasing the level of integration as well as efficiency in programming and erasing. Furthermore, through an increase in the overlapping area between the floating gate and the control gate in each flash memory cell, capacitor coupling is increased and operating voltage is lowered.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a V-shaped flash memory unit. A substrate is first provided, and then a mask layer is formed over the substrate. Using the mask layer as an implant mask, the substrate is doped to form a buried source line in the substrate. The substrate is next etched using the mask layer as an etching mask to form a V-shaped trench that exposes the buried source line. The mask layer is removed. A V-shaped word line stack gate is formed over the V-shaped trench and extends into regions above the substrate on each side. The V-shaped word line stack gate includes a tunnel oxide layer, a floating gate, a dielectric layer and a control gate. A common drain region is formed in the substrate on each side of the V-shaped stack gate. An insulation layer is formed over the substrate, and then a bit line is formed over the insulation layer. A conductive plug is formed in the insulation layer and electrically connects the common drain region and the bit line.
The V-shaped structure of this invention increases the level of integration of flash memory and the overlapping area between the floating gate and the control gate. Hence, capacitor coupling is increased and operating voltage is lowered. In addition, the provision of two channels in the V-shaped structure increases programming and erasing efficiency of each flash memory unit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4085603 (1978-04-01), Vanek
patent: 5569615 (1996-10-01), Yamazaki et al.
patent: 5587332 (1996-12-01), Chang et al.
patent: 5953610 (1999-09-01), Takeuchi
patent: 6087220 (2000-07-01), Rogers et al.
patent: 6096604 (2000-08-01), Cha et al.
Huang Jiawei
J.C. Patents
Luu Pho
United Microelectronics Corp.
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