Semiconductor device having gate edges protected from charge...

Details Semiconductor device having gate edges protected from charge... Semiconductor device having gate edges protected from charge...

2001-04-12

2002-09-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S265000

Reexamination Certificate

active

06455373

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabricating semiconductor memory devices such as EEPROM or flash EEPROM, and more particularly to methods for reducing mobile ion migration into transistor gate sides during semiconductor manufacturing.
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. A common circuit component of flash memory devices is the transistor. In these devices, a transistor is established by forming a gate stack including a control gate and a floating gate on a silicon substrate, and then forming a source region and a drain region in the substrate beneath the gate stack by implanting ion dopants into the areas of the substrate that are to become the source and drain regions. This generally-described structure cooperates to function as a transistor.
After the gate stacks have been formed, subsequent manufacturing steps are undertaken to complete the semiconductor device. These subsequent steps include, among other things, the formation of additional layers of transistors along with interlayer dielectrics (ILD), followed by metallization and external electrical contact formation. It happens, however, that during these subsequent steps, mobile ions and/or other processed-induced charges can migrate into the sides of the floating gate, which undesirably can alter an electrical characteristic of the device, such as the threshold voltage or current, from its design value. This in turn adversely affects the reliability of the transistor. The present invention recognizes this prior art drawback and provides the below-noted solutions.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for establishing plural core gate transistors on a semiconductor substrate. The method includes forming plural core gate stacks on the substrate. The core gate stacks are covered with a first protective layer, portions of which are etched away such that at least intended source regions of the substrate are exposed. Dopant is next implanted into the intended source regions. A second protective layer made of nitride or silicon oxynitride (SiON) is deposited onto the first layer and portions etched away such that at least intended drain portions of the substrate are exposed. Then, dopant is implanted into the intended drain regions to thereby establish plural core transistors. Subsequent manufacturing acts can be undertaken with the first and second layers protecting at least the sides of the core gate stacks from ion migration and, hence, from unwanted charge gain or loss from the floating gate of the gate stack.
In a preferred embodiment, periphery gates are formed on the substrate, and the periphery stacks are covered with the first protective layer. However, etching away of the first protective layer on the periphery gates is prevented during the act of etching away portions of the first layer to expose the intended source regions.
As intended in the preferred embodiment, the first and second layers cover only the sides of the core gate stacks after the second etching act, as well as portions of the periphery gates. The first protective layer can have a thickness of between three hundred Angstroms (300 Å) and one thousand Angstroms (1000 Å) immediately subsequent to forming the first protective layer, and it can be made of a variety of materials such as nitride, SiON, etc.
As set forth in greater detail below, each core gate stack includes a source side and a drain side, and the protective layers on the source sides are thinner than the protective layers on the drain sides. Moreover, the protective layers on the source sides are shorter than the protective layers on the drain sides. A semiconductor device made according to the present method, as well as a computer incorporating the device, are also disclosed.
In another aspect, a method for making a flash memory device includes forming first and second protective shoulders on core gate stacks, such that dopant can be implanted into a substrate supporting the stacks to establish transistors. Charge migration into sides of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, however, by the protective shoulders.
In still another aspect, a semiconductor device includes plural gate stacks, each defining a source side and a drain side. The device also includes inner and outer protective shoulders on both sides of the stacks, whereby migration of charges into the sides is impeded.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.


REFERENCES:
patent: 6127222 (2000-10-01), Luning et al.

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