Method of forming a DRAM cell

Details Method of forming a DRAM cell Method of forming a DRAM cell

2000-10-03

2002-01-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S255000, C438S254000

Reexamination Certificate

active

06340614

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to a method of manufacturing a DRAM cell, and more particularly, to a method of forming a DRAM cell with a capacitor having high capacitance directly over a transistor having a recessed-gate
(2) Description of the Related Art
Integrated circuits (ICs), such as ultra-large scale integrated (ULSI) circuits, can include as many as one billion transistors or more. The ULSI circuits are generally composed of complementary metal oxide semiconductor field effect transistors (MOSFETs). Each MOSFET contains a gate electrode disposed between a drain region and a source region. In order to increase the device density and operating speed of the integrated circuits, the feature size of transistors within the circuits must be shrunk down. Particularly, in scaling down devices, a P-channel or an N-channel with shorter channel length is needed to enhance the operating speed.
Generally, photolithography process is a critical technique for shortening the channel length of a MOSFET. It is believed that the achievable minimum channel length depends on the photolithography limit of the lithographic tool, e.g. a stepper or a scanner.
In order to succeed at sub-0.1 um gate dimensions and below, a recessed-gate MOSFET with out-diffused source/drain extension was disclosed in U.S. Pat. No. 6,093,947. According to this prior art, a semiconductor wafer with a plurality of shallow trench isolation (STI) is provided. A pad oxide layer and a dielectric layer are formed on the semiconductor wafer. Next, a hole is formed in the structure extending into the semiconductor wafer. The hole has sidewalls and a bottom wall. Thereafter, oxide spacer regions are formed on the sidewalls of the hole, wherein the oxide spacer regions contain a dopant material which can out-diffuse when subjected to annealing.
After that, a gate oxide region is formed on the bottom wall of the hole. After that, a conformal layer of polysilicon is formed in the hole and on the dielectric layer, and a CMP process is next performed to remove the portions of the polysilicon layer outside the hole.
Thereafter, the dielectric layer is removed to expose the pad oxide layer and outer walls of the oxide spacer regions. Source/drain regions are next formed in the semiconductor wafer adjacent to the hole.
Finally, an annealing process is performed to cause out-diffusion of the dopant from the oxide spacer regions to the semiconductor wafer so as to form an extension which wraps around the oxide spacer regions and provides a connection to a channel region which is located beneath the gate oxide region. After that, nitride double spacers are formed over the pad oxide layer. Finally, metal contacts are formed in the structure.
However, according to the prior art, two more polysilicon layers above the transistor (such as poly 2/poly 3, or poly 3/poly 4) are needed to form a stacked capacitor for a DRAM cell. The stacked capacitor results in a high topology on the semiconductor substrate, so that the subsequent photolithography and etching processes for patterning the stacked capacitor are difficult to perform. Frequently, this drawback decreases the production yield very much. On the other hand, according to the prior art, an extra trench is needed to form a trench capacitor for a DRAM cell. The trench capacitor wastes a great deal of wafer area, and production cost is thus enlarged. In order to achieve good production yield and low production cost, it will be necessary to develop a new technology for forming a DRAM cell.
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a method of forming a DRAM cell with a capacitor having high capacitance directly over a transistor having a recessed-gate.
It is another object of the present invention to provide a DRAM cell with a capacitor having high capacitance directly over a transistor having a recessed-gate.
A method of forming a DRAM cell with a capacitor having high capacitance directly over a transistor having a recessed-gate is disclosed. First, some isolation regions such as shallow trench isolation (STI) regions are formed in a semiconductor substrate. A heavily-doped region is then formed in the semiconductor substrate. Thereafter, a first dielectric layer and a second dielectric layer are formed on the semiconductor substrate in sequence. The first dielectric layer and the second dielectric layer should have selective etchability. Typically, the first dielectric layer is composed of silicon dioxide, and the second dielectric layer is a thick film and composed of silicon nitride.
A trench is next formed in the semiconductor substrate by an anisotropic etching process. In addition, the source/drain regions of the transistor are also formed in the anisotropic etching process. After that, the first spacers with dopant source material are formed on the sidewalls of the trench. After forming a gate dielectric layer within the trench, a first plug is formed on the gate dielectric layer as a gate plug of the transistor. After forming an isolation film on the first plug, source/drain extensions of the transistor are formed by annealing to out-diffuse the dopant source material contained in the first spacers.
Thereafter, a second plug is formed on the isolation film, so that the top surface of the second plug has the same level with the top surface of the second dielectric layer. After removing the second dielectric layer by performing a wet etching process, the second spacers are formed on the sidewalls of the first spacers. The second spacers are composed of silicon dioxide.
After that, the third spacers are formed on the sidewalls of the second spacers, wherein the third spacers is composed of conductive material, such as doped polysilicon. After removing the second spacers and the upper portions of the first spacers, a capacitor is formed on the transistor.
During the processes of forming the capacitor, a conductive layer is first deposited. Next, the conductive layer is patterned by performing a photolithography process and an etching process to form the lower electrode of the capacitor. After forming the capacitor dielectric, the upper electrode of the capacitor is then formed on the capacitor dielectric.


REFERENCES:
patent: 5789291 (1998-08-01), Sung
patent: 6020236 (1999-02-01), Lee et al.

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