Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-12-14
2002-07-16
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S704000, C216S016000, C216S039000
Reexamination Certificate
active
06420272
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor technology, and more particularly, to methods of defining noble metal electrodes of storage cell capacitors for use in semiconductor random access memory devices using high-permittivity dielectric capacitors.
BACKGROUND OF THE INVENTION
The density of semiconductor random access memory has been increasing at a rapid pace ever since this technology was first introduced. This remarkable increase in density has been brought about by advances in various areas of technology, including lithography, dry patterning, and thin film deposition, and by improvements in DRAM architecture resulting in a more efficient cell utilization. In such a DRAM memory, information is stored as electric charge on a capacitor, and this charge is accessed by a single field effect transistor (FET). As the density of the DRAM memory circuits has increased as indicated, both the amount of circuit area which can be allocated to the storage capacitor and the potential to which the capacitor can be charged has decreased. These two effects result in a reduction in the amount of charge that can be stored by the capacitor. The minimum amount of charge that must be stored in order to obtain reliable operation of the DRAM circuit is determined by the sensitivity limits of sense amplifiers, parasitic capacitance and alpha-particle considerations. Although this minimum amount of charge has decreased through succeeding generations of DRAM design, it is expected that the required storage capacitance will remain nearly constant at 25-40 fF/cell in future generations of DRAMs. Achieving this required capacitance while the physical size of the storage capacitor decreases will be a major challenge in fabricating future generations of DRAMs.
Higher capacitance density can be achieved by the use of: complex electrode structures providing a large surface area within a small lateral area; thinner capacitor dielectric; and higher permittivity capacitor dielectric materials. In general, increasing the surface area, such as, for example, by the use of trench capacitors, leads to increased complexity and hence increased cost. The use of thinner dielectric thickness leads to reduced Voltage capability and decreased reliability. Much work in recent years has focused on the development of high permittivity dielectric materials for use in DRAM storage capacitors.
DRAM circuits manufactured to date contain primarily capacitors fabricated utilizing a thin dielectric layer composed of silicon dioxide and/or a mixture of silicon dioxide and silicon nitride, sandwiched between electrodes made of doped crystalline or polycrystalline silicon. Modifying this material set will break a 25 plus year precedent in which long-term dielectric performance and reliability have been firmly established. Incorporating a high permittivity dielectric material into a DRAM storage capacitor drives the need not only for new dielectric materials, but also for new electrode and barrier materials, and for the processing methods to form and pattern these new materials.
Thin film perovskite materials, such as barium-strontium titanate, have emerged as a leading contender as a dielectric material for future generations of DRAMs. Most schemes for the integration of the perovskite dielectric material into the DRAM structure have used noble-metal or noble-metal-oxide electrodes in combination with a deposited conductive diffusion barrier. The deposited conductive diffusion barrier is required to prevent the inter-diffusion of the electrode material with, and to prevent the diffusion of oxygen into, the silicon elements of the DRAM integrated circuit during the formation of the thin film perovskite material. The noble-metal or noble-metal-oxide electrode material is required to sustain the high temperatures of 550 to 700° C. used during the formation of perovskite films such as barium-strontium titanate. Suitable electrode materials have been found to be noble metals such as Pt, Ir, Ru, and Pd, and noble-metal-oxides such as IrO
2
and RuO
2
.
An important characteristic of the metal electrode material is the ease with which it can be dry etched, in order that techniques can be developed which allow low cost, high quality patterning of the electrodes. For the above listed materials, Ru and RuO
2
are easily dry etched, but such etching requires the use of dangerous materials and also produces dangerous by-products whose presence is not generally desirable in the workplace. The remaining materials are difficult to dry etch due to the absence of any low temperature volatile etch products, a pre-requisite for a low-cost dry etch process. Platinum is typically patterned by reactive ion etching (RIE) using a Cl-based chemistry and a patterned hard mask. Suitable hard mask materials include silicon oxide, silicon nitride, titanium, titanium oxide, and titanium nitride.
A problem arising from the use of this technique is that the hard mask must now be removed from the surface of the remaining platinum electrode. The area of the surface of the semiconductor body surrounding the platinum electrode is an insulator, typically silicon oxide or silicon nitride, materials which have similar etch characteristics and properties as the hard mask materials which must be removed from the top surface of the platinum electrode. Any simple process which removes the hard mask from the surface of the platinum electrode will also remove some of the insulting material surrounding the electrode, resulting in a degradation of this surface and a potential problem with undercutting of the platinum electrode.
It is desirable to provide a method of fabricating semiconductor random access memory circuits containing storage capacitors utilizing high permittivity dielectric materials in which the requisite noble metal electrode structures are formed without undue damage to the surrounding insulator surfaces and without the introduction of undesirable undercutting of the electrodes.
SUMMARY OF THE INVENTION
We have found that the fabrication of semiconductor random access memory circuits containing storage capacitors fabricated using thin film perovskite materials such as barium-strontium titanate can be simplified, and made more controllable and reliable, if hard mask materials used in the process of defining noble metal electrodes are removed using the inventive method of fabrication described herein. The present inventive method of fabrication makes use of the original tool set and materials used to fabricate conventional random access semiconductor memory circuits with only minor changes to the conventional process flow.
After the electrode is patterned, a layer of material, such as photoresist, or other spin-coated film or reflowable material, is used to protect the region surrounding the hard mask material while the hard mask material is etched. The photoresist is applied in a manner such that the protective photoresist is self-aligned to the hard mask material, and no additional lithography steps are required to define the masking photoresist. Additional intermediate layers of dielectric may also be used to provide adherence.
The photoresist material is applied to the semiconductor wafer as a liquid which will form a planar surface. Subsequent drying processes may result in some loss of planarity of this surface. If this loss of planarity is excessive, the surface of the photoresist may be again planarized by the use of processes such as chemical mechanical polishing (CMP). Because the surface of the photoresist is planar, the thickness of photoresist over the noble metal electrode and the covering hard mask is thinner than the thickness of photoresist over the region surrounding the noble metal electrode. An amount of photoresist material equal to the thickness of the photoresist over the noble metal electrode is removed from the surface of the photoresist. This exposes the surface of the hard mask while leaving photoresist in the region surrounding the noble metal electrode. The hard mask material can now be etched so as to expose th
Athavale Satish D.
Chaudhary Nimal
Kotecki David Edward
Kunkel Gerhard
Lian Jenny
Braden Stanton
Infineon Technologies A G
Kunemund Robert
LandOfFree
Method for removal of hard mask used to define noble metal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for removal of hard mask used to define noble metal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for removal of hard mask used to define noble metal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2825003