Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-26
2002-09-10
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000
Reexamination Certificate
active
06448615
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention concerns integrated circuits that include field-effect transistors, particularly metal-oxide-semiconductor field-effect transistors.
Integrated circuits, the key components in thousands of electronic and computer products, are interconnected networks of electrical components fabricated on a common foundation, or substrate. Fabricators typically use various techniques, such as layering, doping, masking, and etching, to build thousands and even millions of microscopic transistors, resistors, and other electrical components on a silicon substrate, known as a wafer. The components are then “wired,” or interconnected, together to define a specific electric circuit, such as a computer memory.
Many integrated circuits include a common type of transistor known as a metal-oxide-semiconductor, field-effect transistor, or “mosfet” for short. A mosfet has four electrodes, or contacts—specifically, a gate, source, drain, and body. In digital integrated circuits, such as logic circuits, memories, and microprocessors which operate with electrical signals representing ones and zeroes, each mosfet behaves primarily as a switch, with its gate serving to open and close a channel connecting its source and drain. Closing the switch requires applying a certain threshold voltage to the gate, and opening it requires either decreasing or increasing the gate voltage (relative the threshold voltage), depending on whether the channel is made of negatively or positively doped semiconductive material.
Mosfets are the most common transistors used in integrated-circuit memories, because of their small size and low power requirements. Integrated-circuit memories typically include millions of mosfets operating simultaneously, to store millions of bits of data. With so many mosfets operating simultaneously, the power consumption of each mosfet is an important concern to memory fabricators. Moreover, as fabricators continually strive to pack more and more mosfets into memory circuits to increase data capacity, the need for even lower power and lower voltage mosfets compounds.
Conventional mosfets operate with power supply voltages as low as two volts. Although lower supply voltages are desirable, fabricators have reached a technical impasse based on their inability to make millions of mosfets with perfectly identical threshold voltages. Hence, each of the mosfets has its own unique threshold voltage, with some deviating only slightly from the fabricator's intended threshold voltage and others deviating significantly. The typical range of threshold voltages in memory circuits extends from 0.2 volts above to 0.2 volts below the intended threshold voltage.
Thus, for example, if fabricators build mosfets with an intended threshold of one-quarter volt to accommodate half-volt power supplies, some mosfets will actually have a threshold around 0.4 volts and others around 0.05 volts. In practice, these deviant mosfets are prone not only to turn on and off randomly because of inevitable power-supply fluctuations or electrical noise affecting their gate voltages, but also to turn on and off at widely variant rates. Therefore, to avoid random operation and promote uniform switching rates, fabricators raise the intended threshold to a higher level, which, in turn, forecloses the option of using lower power-supply voltages.
Recently, three approaches involving the concept of a dynamic, or variable threshold voltage, have emerged as potential solutions to this problem. But, unfortunately none has proven very practical. One dynamic-threshold approach directly connects, or shorts, the gate of a mosfet to its body causing the mosfet to have a lower effective threshold during switching and higher threshold during non-switching periods. (See, Tsuneaki Fuse et al., A 0.5V 200 MHZ 32 b ALU Using Body Bias Controlled SOI Pass-Gate Logic, IEEE International Solid State Circuits Conference, San Francisco, pp. 292-93, 1997.) However, this approach forces the mosfet to draw significant power even when turned off, in other words, to run continuously. This poses a particularly serious limitation for battery-powered applications, such as portable computers, data organizers, cellular phones, etc.
Louis Wong et al. disclose another dynamic-threshold approach which capacitively couples an n-channel mosfet's gate to its body. (See Louis Wong et al., A 1V CMOS Digital Circuits with Double-Gate Driven MOSFET, IEEE International Solid State Circuits Conference, San Francisco, pp. 292-93, 1997.) Implementing this approach requires adding a gate-to-body coupling capacitor to every mosfet in a memory circuit. Unfortunately, conventional integrated-circuit capacitors are planar or horizontal capacitors that consume great amounts of surface area on an integrated-circuit memory, ultimately reducing its data capacity.
The third dynamic-threshold approach, referred to as a synchronous-body bias, applies a voltage pulse to the body of a mosfet at the same time, that is, synchronous, with the application of a voltage to the gate, thereby reducing its effective threshold voltage. (See Kenichi Shimomuro et al., A 1V 46 ns 16 Mb SOI-DRAM with Body Control Technique, Digest of the IEEE International Solid-State Circuits Conference, San Francisco, pp. 68-69, 1997.) Unfortunately, implementing the circuitry to apply the synchronous voltage pulse requires adding extra conductors to carry the voltage pulses and possibly even built-in timing circuits to memory circuits. Thus, like the previous approach, this approach also consumes significant surface area and reduces data capacity.
Accordingly, there is a need to develop space-and-power efficient implementations of the dynamic threshold concept and thus enable the practical use of lower power-supply voltages.
SUMMARY OF THE INVENTION
To address these and other needs, embodiments of the present invention provide a space-saving structure and fabrication method for achieving gate-to-body capacitive coupling in n-and p-channel field-effect transistors. Specifically, one embodiment of the invention uses at least one vertical, that is, non-horizontal, capacitive structure, to achieve the gate-to-body capacitive coupling. In contrast to conventional horizontal capacitor structures, the vertical structure requires much less surface area. Moreover, for further space savings, another embodiment not only uses a lateral semiconductive surface of the transistor as a conductive plate of the gate-to-body coupling capacitor, but also places the other conductive plate in a normally empty isolation region between neighboring transistors. The space-saving gate-to-body capacitive coupling of the invention yields practical transistors with superior switching rates at low-operating voltages, ultimately enabling practical half-volt inverters, buffers, sense amplifiers, memory circuits, etc.
Another aspect of the invention concerns a method for making a field-effect transistor having gate-to-body capacitive coupling. One embodiment entails forming an NMOS or PMOS device island and then growing dielectric sidewalls on two opposing sidewalls of the NMOS or PMOS device island. Afterward, the method forms conductive sidewalls on the dielectric sidewalls. This method yields two vertical gate-to-body coupling capacitors, one on each of the two opposing sidewalls of the device island. In other embodiments, the method isolates the device island from an underlying substrate to form a silicon-on-insulator structure and forms self-aligned source and drain regions.
Still other aspects of the invention include circuits for half-volt inverters, voltage-sense amplifiers, and memories. Each incorporates a field-effect transistor having vertical gate-to-body capacitive coupling and thus offers not only space savings but also superior switching rate at low voltages.
REFERENCES:
patent: 3461361 (1969-08-01), Delivorias
patent: 4450048 (1984-05-01), Gaulier
patent: 4521448 (1985-06-01), Sasaki
patent: 4673962 (1987-06-01), Chatterjee et al.
patent: 4751561 (1988-06-01), Jastrzebski
patent: 4922315
Forbes Leonard
Noble Wendell P.
Micro)n Technology, Inc.
Prenty Mark V.
Schwegman Lundberg Woessner & Kluth P.A.
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