Low thermal budget method for forming MIM capacitor

Details Low thermal budget method for forming MIM capacitor Low thermal budget method for forming MIM capacitor

2001-04-20

2002-09-17

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S399000

Reexamination Certificate

active

06451650

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the general field of capacitors in integrated circuits with particular reference to devices wherein capacitance is raised through an increase in the base electrode area, as opposed to multi-layering.
BACKGROUND OF THE INVENTION
As the areas of storage electrodes used with DRAMs (dynamic random access memory) continue to decrease in order to match the increase in DRAM density, a large variety of stack structures have been developed by a number of researchers. These include the box, the fin, the crown, the spread, and the cylinder families. However, the capacitance of these stack structures cannot easily satisfy the capacitance requirements of 256M or 1G DRAM units, within their limited design rules.
It is generally agreed that high dielectric constant materials will be needed for use in 1G or 4G DRAMs. Metal insulator metal (MIM) capacitor structures, used in combination with high dielectric constant materials such as Ta
2
O
5
, become the structures of choice for these future DRAM technologies. MIM capacitor structures have the advantage of low interfacial reaction (thereby raising capacitance) but, in the general case, it is very difficult to increase the surface area of a metal electrode.
The prior art relating to ways to increase the surface area of a metal electrode was therefore routinely searched with the following references of interest being found:
U.S. Pat. No. 6,074,913 (Lou et al.) shows a capacitor process that comprises: 1) forming a tungsten bottom electrode which is coated with successive layers of titanium nitride and silicon oxide, 2) forming HSG (hemispherical grains) of silicon, which are used as a mask to etch the silicon oxide and titanium nitride layers converting them into a hard mask 3) after removal of the HSG, anisotropically etching the tungsten layer through said hard mask to form a bottom electrode (having no sidewalls). Lou give very little detail on how they form HSG except to note that CVD (chemical vapor deposition) of polysilicon is normally done using silane.
U.S. Pat. No. 6,057,205 (Wu) teaches a capacitor structure that is similar to that formed by the process of the present invention in that it also has sidewalls, but the total amount of heat energy (thermal budget) that is required to execute the Wu process is significantly higher than that required for the process of the present invention. Unlike the present invention, Wu uses silane to deposit the HSG and uses oxidation, rather than etching, to increase the surface area of the base electrode.
U.S. Pat. No. 5,966,612 (Wu), U.S. Pat. No. 5,650,351 (Wu), and U.S. Pat. No. 5,960,280 (Jenq et al.) all show capacitor formation processes that make use of HSG silicon.
The present invention describes an improved HSG-based process that does not use silane and which requires a significantly lower thermal budget than do processes of the prior art. The latter feature is particularly important because, for advanced DRAMs (over 1 Gb per chip), a metal gate is used instead of the conventional polysilicon gate and the gate oxide is a high K material rather than silicon oxide. The use of a metal gate comes with the constraint that a lower processing temperature is required if high yield and reliability are to be retained. Another important feature of the present invention (which is not present in the prior art) is improved control of the HSG sizes and separations.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for the manufacture of a capacitor for use as part of a DRAM structure in an integrated circuit.
Another object of the invention has been that said process require the expenditure of a low thermal budget relative to similar processes of the prior art in order to guarantee high yield and reliability.
A further object has been that the process provide improved control over the sizes and separations of the HSGs that are used as masks within the process.
A still further object has been that said HSGs be used as a contact mask rather than for the formation of a hard mask.
Yet another object has been that the base pedestal of the capacitor be isotropically etched using a dry chemical etch rather than anisotropically using a reactive ion etch.
These object have been achieved by using a material other than silicon for the base electrode so that the HSGs can be used directly for masking. By using disilane, rather than the more conventional silane, the HSGs can be formed at significantly lower temperatures and their size and mean separation can be well controlled. With the HSGs in place, the base electrode is etched so that its surface area is significantly increased. After removal of the HSGs, a suitable dielectric layer may be laid down, including high K materials such as barium strontium titanate, and the capacitor completed with the deposition of a suitable top electrode.


REFERENCES:
patent: 5464791 (1995-11-01), Hirota
patent: 5650351 (1997-07-01), Wu
patent: 5960280 (1999-09-01), Jeng et al.
patent: 5966612 (1999-10-01), Wu
patent: 6057205 (2000-05-01), Wu
patent: 6074913 (2000-06-01), Lou et al.
Byoung Taek Lee et al., “Integration of (Ba, Sr)TiO3Capacitors with Platinum Electrodes Having SiO2Spacer,” IEEE 1997, IEDM 97-249, pp. 10.2.1-10.2.4.

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