Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1996-11-19
2002-03-19
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S025000
Reexamination Certificate
active
06360340
ABSTRACT:
This invention relates generally to automatic test equipment and more specifically to automatic test equipment used in the manufacture of semiconductor memories.
Semiconductor memories are tested during their manufacture with automatic test equipment. The test indicates which cells within the memory are faulty. To test a memory very quickly, the results of the test on each cell are stored in a very fast memory inside the tester called a catch RAM. This information is then accessed, either at a later time or by other circuitry.
Information about faulty cells is used in many different ways. It might, for example, be used in process control. The number or position of the faults in a memory can indicate a problem with the manufacturing process. The fault information might be stored in a non-volatile memory for later processing or graphically displayed for a human operator. Usually, the fault information is displayed in a two dimensional array, with the position of a faulty cell in the display correlating with the physical position of that cell on the surface of the memory chip. Clusters or patterns of faults might be recognized and used to identify problems in the manufacturing process. In this way, adjustments might be made to the memory manufacturing process to improve the process yield.
A difficulty with displaying fault information graphically is the amount of information that must be transferred to a display device is very large. The transfer process is therefore very slow. For example, a typical memory size is 64 Megabits. Even if a bit of data can be passed every 2 microseconds, the total time to transfer all the information to the display device is on the order of 2 minutes.
Two minutes is a very long time during a semiconductor manufacturing operation. To meet throughput targets for memory manufacture, a memory should be tested in a matter of seconds. One way that the data transfer time is reduced is through the use of lossy compression. Lossy compression is performed by combining groups of adjacent cells into one bit of data. If any cell in the group is faulty, the entire group is indicated as faulty. A typical grouping might combine sixteen cells into one group. However, even with this amount of compression, the transfer time from the catch RAM to the display might still be about eight seconds, which is a long time. In addition, if more detailed analysis of the faults within the memory is required, the data required for the analysis is not available.
A further problem with display of information in current memory testers is that the data is not always in an easily comprehensible form. One of the main reasons for graphically displaying failure information in a memory tester is to allow quick identification of problems in the memory manufacturing process.
It would be highly desirable to increase the transfer rate of data to a display processor in a memory tester so that the time required to present information on a memory being tested is very short. It would also be desirable to be able to present the data in a fashion that allowed problems to be identified more readily.
SUMMARY OF THE INVENTION
With the foregoing background in mind, it is an object of the invention to provide lossless compression of data within a memory tester.
It is also an object to provide multiple display formats of data in a memory tester.
The foregoing and other objects are achieved in a semiconductor memory tester with data transfer circuitry coupled to a display having a lossless compressor. In a preferred embodiment, the lossless compressor is a run length encoder.
In an alternative embodiment, the data compression circuit includes a plurality of display memories and a gating circuit. The contents of one memory can be used as an input to the gating circuit to control storage of information in another memory. In one embodiment, the gating circuit can be controlled to accumulate in one of the memories failures detected during tests of multiple parts. In another embodiment, the gating circuit is controlled to store in one of the memories failures that appear when the same part is tested under different conditions.
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Brown Benjamin J.
Donaldson John F.
Gage Robert B.
Joffe Alexander
Iqbal Nadeem
Kreisman Lance M.
Teradyne, Inc.
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