Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2000-07-20
2002-03-12
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S017000, C331S025000, C331S010000
Reexamination Certificate
active
06356159
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the technical field of frequency synthesizers, and in particular, it relates to a frequency synthesizer that can accurately compensate for ripple current.
BACKGROUND OF THE INVENTION
The cellular telephone is a multi-frequency channel access system, and in order to shift the frequency being used for an open channel, a frequency synthesizer that can provide high-speed lock up is necessary.
The encoder
101
of
FIG. 6
is a conventional device of this type of frequency synthesizer, and a PLL (phase-locked loop) circuit is used for the frequency divider system.
This frequency synthesizer
101
is provided within a semiconductor integrated circuit device that forms a transmit/receive circuit for a cellular telephone, and it has an oscillator
131
, a frequency divider
132
, a reference clock signal generator
133
, a phase comparator
134
, a charge pump circuit
135
, a low-pass filter
136
, and a control circuit
138
. Within the oscillator
131
, an external output signal (OUT) of a prescribed frequency is generated, and that external output signal (OUT) is output to the frequency divider
132
and to other circuits within the semiconductor integrated circuit device in which this frequency synthesizer
101
is provided.
The frequency divider
132
frequency divides the external output signal (OUT) that is input, generates a comparison signal, and outputs this comparison signal to the phase comparator
134
. The said phase comparator
134
compares the phase of the comparison signal that is input from the frequency divider
132
and a reference clock signal that is input from the reference clock signal generator
133
, and outputs a signal corresponding to the phase difference to the charge pump circuit
135
. The charge pump circuit
135
, based on the signal corresponding to the input phase difference, supplies an output signal, and that output signal is output to the oscillator
131
as a control signal via the low-pass filter
136
.
The oscillator
131
changes the frequency of the external output signal (OUT) by means of this input control signal, and it is controlled so that the phase of the comparison signal matches the phase of the reference clock signal. As a result, the frequency of the external output signal (OUT) becomes the value of the frequency of the reference clock signal multiplied by the divisor value of the frequency divider
132
.
The above-mentioned frequency divider
132
is controlled by means of the control circuit
138
, and it is constructed so that the divisor value changes cyclically, for example, for the case where the frequency of the reference clock signal is 200 KHz, the value for seven cycles (35 &mgr;sec) is 5000, and the value for one cycle (5 &mgr;sec) is 5001, the average divisor value in which eight cycles are averaged becomes 5000.125 (=5000+⅛). Therefore, the frequency of the external output signal (OUT) is locked at the average divisor value multiplied by the reference clock signal, which is 1000025 KHz.
During eight cycles, if the divisor value for six cycles is 4000, and the divisor value for two cycles is 4001, the average divisor value is 4000.25, and the frequency of the external output signal (OUT) becomes 800.050 MHz.
In this way, if the average divisor value has values in columns to the right of the decimal point, narrow channel spacings of 25 KHz, 12.5 KHz, and the like, become possible for high frequencies such as 800 MHz and 1 GHz.
However, if the divisor value is cyclically changed as mentioned above, even after the external output signal (OUT) is locked at the desired frequency, the phase of the comparison signal and the phase of the reference clock signal are not completely synchronized, and a phase difference is generated. This phase difference is the cause of a cyclically changing ripple current within the signal that is output from the phase comparator
134
.
The ripple current within the signal output from the phase comparator
134
causes the generation of transient components in the external output signal (OUT), which not only deteriorates reception characteristics of communications equipment such as cellular telephones, but it is also a source of interference during transmission, so ripple current is an enormous problem.
Thus, the compensating circuit
137
is provided in the above-mentioned frequency synthesizer
101
. Within the compensating circuit
137
, the amount of compensating current is set beforehand, and when a control signal from the control circuit
138
is input to the compensating circuit
137
, a compensating current of the predetermined current amount is superimposed on the output signal of the charge pump circuit
135
at the timing at which that control signal is input, so that the ripple current can be removed, and so that an external output signal (OUT) without any transient components can be output.
The waveform of the ripple current and the compensating current contained in the output signal of the charge pump circuit
135
are respectively shown as symbols (a, b) in FIG.
7
. The ripple current (a) changes cyclically as shown in
FIG. 7
, and the compensating current (b) also changes cyclically so as to follow the changes of the ripple current (a).
At this time, even if a compensating current (b) is generated that is equal to the size of the ripple current (a), if the generation time of the ripple current and the output time of the compensating current are not synchronized, as shown by symbol (c) in
FIG. 7
, the ripple component of the output signal of the charge pump circuit on which the compensating current is superimposed does not become zero, and there is the problem that the transient component cannot be removed accurately.
The present invention was created for the purpose of solving the unfavorable circumstances of the above-mentioned prior art, and its purpose is to offer technology which can accurately compensate for ripple current.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems, the present invention has an oscillator that controls the frequency of an output signal according to a voltage control signal, a frequency divider that divides the above-mentioned output signal according to a frequency division value that changes cyclically and generates a comparison signal, a phase comparator that generates a phase difference signal by comparing the phase of the above-mentioned comparison signal and the phase of a reference clock signal, a delay circuit that generates and applies a delay to the above-mentioned phase difference signal, a charge pump circuit that generates a control signal corresponding to the phase difference signal that is output from the above-mentioned delay circuit, a low-pass filter that executes a prescribed wave filtering process on the above-mentioned control signal and outputs a voltage control signal, a compensating circuit that superimposes a compensating current on the above-mentioned control signal according to compensation voltage data, a detecting circuit that detects the output time of the above-mentioned control signal from the above-mentioned voltage control signal and the output time of the above-mentioned compensating current, and outputs a detection signal, wherein the above-mentioned delay circuit controls the supply of the above-mentioned compensating voltage data to the above-mentioned compensating circuit so that the output time of the above-mentioned control signal and the output time of the above-mentioned compensating current are synchronized.
One aspect of the present invention is based on the frequency synthesizer in which the detecting circuit, within one cycle at the time of the above-mentioned cyclic frequency divider, detects the time difference between the output time of the above-mentioned control signal and the output time of the above-mentioned compensating current by means of the above-mentioned voltage control signal that contains the above-mentioned superimposed compensating current and that is output at two times that bracket the ti
Grimm Siegfried H.
Kempler William B.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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