Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-16
2002-01-15
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S981000
Reexamination Certificate
active
06339001
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the formation of semiconductor devices and more particularly to a method and structure which includes gate oxides having multiple thicknesses.
2. Description of the Related Art
Conventional systems such as those shown in U.S. Pat. Nos. 5,444,279 and 5,489,577 (incorporated herein by reference) manufacture gate oxides using methods that incorporate an impurity implant patterned with a photoresist mask to form multiple thicknesses of gate oxides. They also use enhanced oxidation by Boron doping. This is not useful for advanced CMOS devices because the high doping in the channel can adversely affect the threshold voltage of the device.
More specifically, such conventional systems use photoresists to selectively implant an impurity and then either remove or form a gate oxide over the regions having different impurity levels. The impurities cause the oxide to grow (or be removed) at a different rate and permit a gate oxide with different thicknesses to be manufactured.
The different gate oxide thicknesses allow different gates or different portions of the gate to be closer to the underlying silicon substrate, which results in decreased coupling between the gate and the transistor channel region. Such processes also make the devices easier to program because the higher impurity concentrations increase the number of hot electrons available in some situations. The thicker gate oxides provide better insulation for a floating gate and reduce the number of electrons which may leak from the floating gate. This increases the charge storage ability of a floating gate and improves the reliability of the device.
However, these processes typically expose the gate oxide to impurities from the photoresist. More specifically, sodium, potassium, iron, nickel, etc. are transferred from the photoresist to the underlying gate oxide. These impurities affect the threshold voltage of the gate oxide, leading to variations in the transistor current-voltage characteristics. Further, high concentrations of these impurities can lead to high leakage currents through the gate oxide, degrading yield and reliability. Therefore, it is difficult to make manufacturing changes to compensate for the impurities and is also difficult to calculate the effect the impurities will have upon the threshold voltage of the gate oxide. Thus, there is a need to eliminate such photoresist impurities from the gate oxide during the formation of multi-thickness gate oxides.
The invention described below forms multiple gate film thickness without exposing the gate oxide to the photoresist. Therefore, the invention produces a structure with different gate oxide thicknesses without suffering the disadvantages of conventional processes.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for forming an integrated circuit chip having multiple-thickness gate dielectrics. The method includes forming a gate dielectric layer over a substrate, forming a sacrificial layer over the gate dielectric layer, forming first openings through the sacrificial layer to expose the gate dielectric layer in the first openings, growing a first gate dielectric having a thickness greater than that of the gate dielectric layer in the first openings, depositing a first gate conductor above the first gate dielectric in the first openings, forming a second opening through the sacrificial layer to expose the gate dielectric layer in the second opening, and depositing a second gate conductor in the second opening.
The structure and method include forming shallow trench isolation regions within the substrate wherein the first opening and the second opening are formed between the shallow trench isolation regions which form a first sacrificial layer and a second sacrificial layer over the first sacrificial layer. The first sacrificial layer is the material that is selectively etchable with respect to the gate dielectric layer. After depositing the second gate conductor, the first sacrificial layer is removed so that the second sacrificial layer is simultaneously removed. After depositing the first gate conductor the sacrificial layer is planarized. The first gate conductor has a thickness less than that of the second gate conductor.
The invention also includes a process for forming an integrated circuit chip having multiple-thickness gate dielectrics which includes forming gate mandrels on a substrate, forming an insulator between the gate mandrels, selectively removing first ones of the gate mandrels to form first openings in the insulator, forming a first gate dielectric within the first openings, depositing a first gate conductor within the first openings and above the first gate dielectric, selectively removing second ones of the gate mandrels to form second openings in the insulator, forming a second gate dielectric within the second openings (the second gate dielectric having a thicknesses less than the first gate dielectric), and depositing the second gate conductor within the second openings above the second gate dielectric.
The inventive structure comprises an integrated circuit chip with first devices having a first gate dielectric with a first gate dielectric thickness, second devices having a second gate dielectric with a second gate dielectric thickness less than the first gate dielectric thickness, wherein the first gate dielectric and the second gate dielectric are free of photoresist impurities.
REFERENCES:
patent: 5057449 (1991-10-01), Lowrey et al.
patent: 5444279 (1995-08-01), Lee
patent: 5498577 (1996-03-01), Fulford, Jr. et al.
patent: 5668035 (1997-09-01), Fang et al.
patent: 5821169 (1998-10-01), Nguyen et al.
patent: 5882993 (1999-03-01), Gardner et al.
patent: 5926708 (1999-07-01), Martin
patent: 6080682 (2000-06-01), Ibok
patent: 6117736 (2000-09-01), Kapoor
patent: 6165849 (2000-12-01), An et al.
patent: 58-100450 (1983-06-01), None
patent: 10326837 (1997-12-01), None
Bronner Gary B.
Gambino Jeffrey P.
Blecker, Esq. Ira D.
International Business Machines - Corporation
McGinn & Gibb PLLC
Trinh Michael
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