Silicon carbide CMOS channel

Details Silicon carbide CMOS channel Silicon carbide CMOS channel

2001-06-29

2002-03-19

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S931000

Reexamination Certificate

active

06358806

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit processing. More particularly the invention relates to a method for forming a silicon carbide channel in a complimentary metal oxide integrated circuit.
BACKGROUND
As integrated circuits become more complex, there is incentive to reduce the surface area required on the substrate for the integrated circuit. Reducing the size of the integrated circuit tends to hold the die size to a reasonable level, and the device also tends to be operable at a higher speed. Unfortunately, as the size of integrated circuits is reduced, limits and constraints in regard to the proper operation of various device structures are encountered.
For example, one of the fundamental challenges for developing integrated circuits is optimizing the speed at which the integrated circuit operates. Because the mobility of holes tends to be lower than the mobility of electrons in many semiconducting materials, the drive current of PMOS transistors tends to be commensurately lower than the drive current of a similarly sized NMOS device, when each is driven at equal supply voltage potentials. Thus, the low drive current of the PMOS device tends to be one speed limiting parameter in certain integrated circuits, such as a logic inverter.
One method of compensating for this situation is to form larger PMOS devices, relative to the size of the NMOS devices. Thus, the larger PMOS structure has an ability to carry a commensurately larger drive current at the same supply voltage potential, because of the increased numbers of carriers. Unfortunately, addressing the problem by increasing the size of the PMOS structures is in direct opposition to the design goal of creating ever smaller integrated circuits.
Another method of compensating for the speed difference is to increase the drive current of the PMOS device by increasing the potential of the supply voltage at which it is driven, relative to that of the NMOS device. Unfortunately, it is often desirable to drive both the PMOS devices and the NMOS devices at the same potential. Thus, compensating for the difference in drive currents between the two structures in this manner is somewhat unsatisfactory. Further, if the higher drive potential is available on the die, then there is a desire to use it to drive the NMOS device at an even greater drive current. Therefore, providing different supply voltages to the different devices to balance the drive currents of the devices tends to be somewhat of an inelegant solution. Additionally, increasing the supply voltages may jeopardize the reliability of the devices due to hot carrier injection into the gate dielectric.
What is needed, therefore, is a structure and a method for its formation that can be used in PMOS and NMOS devices to achieve high drive currents and keep leakage currents low.
SUMMARY
The above and other needs are met by a method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon carbide channel layer and a silicon capping layer on the substrate. A gate insulation layer is formed on top of the silicon capping layer, the gate insulation layer preferably formed at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. The substrate is amorphized using a species such as silicon, germanium, or argon. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source drain dopant is impregnated into the substrate, and activated with a second laser anneal.
Thus, by use of the strained silicon carbide channel layer the mobility of electrons and holes is increased by up to about seventy-five percent when applied to a one hundred nanometer technology. However, the use of strained silicon carbide imposes some limitations in the applied thermal budget once the strained silicon carbide layer is formed. If the strained silicon carbide layer is annealed at a temperature higher than about eight hundred and fifty centigrade, then the layer tends to relax and loose it favorable conduction properties. Therefore, the subsequent layers are formed at temperatures that are preferably below about eight hundred centigrade. Further, laser annealing is s preferably used for locally activating both the low dose drain dopant and the source drain dopant. Because the strained silicon carbide layer tends to have a lower thermal conductivity than that of the substrate, the heat generated by the laser pulses tends to not anneal the strained silicon carbide channel layer during the laser annealing. Annealing by other more traditional methods, such as rapid thermal annealing or furnace annealing to activate the implanted dopants, would tend to exceed the thermal budget of the strained silicon carbide channel layer.
In various preferred embodiments the strained silicon carbide channel layer is formed such as by deposition with a chemical vapor deposition process or growth with a surface reaction epitaxy process. The strained silicon carbide channel layer further is formed to a thickness of preferably about three hundred angstroms, and exhibits a tensile strain. The strained silicon carbide channel preferably has a composition Si
(1−y)
C
y
where y is as high as about two tenths. Further, the strained silicon carbide channel layer for an NMOS device is preferably formed with an in situ boron dopant at a concentration of about 10
17
atoms per cubic centimeter. Still further, an additional dopant may be implanted into the strained silicon carbide channel layer after it is formed. PMOS device s are preferably formed with dopants compatible with PMOS designs, and with concentrations commensurate with such designs.
In a most preferred embodiment, after the step of activating the low dose drain extension dopant with the first laser anneal, an insulating layer is formed around the gate electrode at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal. Thus, standard materials for the spacer, such as silicon oxide or silicon nitride are not preferred for this application, because they tend to be transparent to the laser beam emissions.
Most preferably the insulating layer around the gate electrode is formed of silicon oxide and the spacer material is formed of polysilicon. In other preferred embodiments, the substrate is silicon, the gate insulation layer is silicon oxide, and the gate electrode is polysilicon.
According to another aspect of the invention, a integrated circuit device is described, the improvement being a strained silicon carbide channel layer and a spacer around the gate electrode formed of a material that is reflective to the laser anneal.


REFERENCES:
patent: 5510630 (1996-04-01), Agarwal et al.
patent: 5641695 (1997-06-01), Moore et al.
patent: 6271066 (2001-08-01), Yamazaki et al.

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