Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-08
2002-01-08
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S286000
Reexamination Certificate
active
06337250
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and a process for fabricating the same. In particular, the present invention relates to a technique for preventing quality degradation resulting from “charge-up” incurred when impurity ions are implanted into the source or drain forming regions of a semiconductor device.
BACKGROUND ART
It is generally known in the art that, in fabricating a MOS type semiconductor device, a field oxide layer (i,e. LOCOS layer) is first formed on a silicon substrate, followed by depositions of a gate insulation layer and then a gate electrode on top of the gate insulation layer. Subsequently, impurities such as arsenic or phosphorus are ion implanted into a source forming region and a drain forming region of the device.
Also known in the art is a floating gate type, non-volatile semiconductor memory device. Fabricating non-volatile memory cells based on stacked-structure MOS elements typically involves steps of first forming a field oxide layer (LOCOS layer) on a silicon substrate, depositing in succession a tunnel oxide layer and a floating gate in an active region, followed by depositions of an intermediary dielectric layer and a control gate on top of the floating gate, and thereafter implanting impurity ions such as arsenic into a source forming region and a drain forming region of the device.
When ion implantation is performed for either the MOS type semiconductor device mentioned above or a semiconductor device having a multi-layered gate electrode such as the floating gate type non-volatile semiconductor memory device, a resist layer covering the entire wafer is prepared. Such a resist layer has openings only at implanting areas corresponding to where the sources or drains are to be formed, through which ions are implanted while masking the remainder.
However, the prior art fabrication method such as above has presented a problem in that the gate insulation layer is degraded by a phenomenon called “charge-up”, when performing an ion implantation into the source or drain forming regions. The ion implantation causes charges to flow through the edges of the resist layer openings into the gate insulation layer, causing such problems as dielectric breakdown or creation of a large amount of electrically neutral electron traps in the gate insulation layer, which causes the threshold voltage to be undesirably high. The problems become more pronounced particularly when the gate insulation layer is thinner. While it is pointed out that these problems may possibly be corrected by high temperature annealing provided after the ion implantation, raising the processing temperature will hinder fabrication of a higher performance LSI.
Moreover, in flash memory cells as exemplified by a stacked-structure EPROM, EEPROM, and the like, charge-up occurring at the time of ion implantation may cause defects in data retention characteristics such as a single-bit charge loss, which has been another cause for concern over quality reliability. Specifically in a non-volatile memory cell, the life of a tunnel oxide layer, i.e. the charge through the oxide Qbd to bring the tunnel oxide layer to breakdown, is lower than the intrinsic charge quantity Qi as determined by factors such as the forming method for the oxide layer, by the amount equivalent to a charge quantity Qp (process-induced charge) that passes through the tunnel oxide layer in the fabrication processes after the formation of the tunnel oxide. As a result, the number of programming/erase operations available for a non-volatile memory cell related to the charge through the oxide Qbd is limited, and degradation (single-bit charge loss) in data retention characteristics may occur.
To overcome such quality degradation problems resulting from charge-up at the time of the ion implantation, a method is proposed wherein the ion implantation is performed after forming an insulating layer on a sidewall portion of the floating gate facing the source (see Japanese Patent Application Laid-open No. 7-202046/1995). However, such a technique requires a separate step of forming the sidewall insulation layer, making the fabrication process more complicated.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a semiconductor device which has excellent data retention characteristics, and a method of fabricating such a semiconductor device by a simple process, without creating additional fabrication steps, while avoiding the gate insulation layer quality degradation resulting from charge-up at the time of ion implantation.
A fabrication method of a semiconductor device containing MOS elements in accordance with the present invention comprises the steps of: forming a gate insulation layer on a semiconductor substrate; forming a gate electrode on the gate insulation layer; and implanting impurity ions into source and drain forming regions, wherein the ion implantation into the source and drain forming regions is performed in separate ion implanting steps, and
in at least either one of the ion implantation steps for the source forming region or for the drain forming region, a resist layer used for blocking impurities is provided with a wall extending to the gate insulation layer at a location distant from the gate electrode.
Furthermore, a fabrication method of a semiconductor device including MOS elements in accordance with the present invention comprises the following steps (a) through (h):
(a) a step of forming a gate insulation layer on a semiconductor substrate;
(b) a step of forming a gate electrode on the gate insulation layer;
(c) a step of forming a first resist layer for masking an area other than a first ion implantation area including at least on of a source forming region and a drain forming region, wherein the first resist layer is provided with a wall extending to the gate insulation layer;
(d) a step of forming at least one of a source region and a drain region by implanting impurity ions into the first ion implantation area;
(e) a step of removing the first resist layer;
(f) a step of forming a second resist layer for masking an area other than a second ion implantation area including at least one of a drain forming region and a source forming region;
(g) a step of forming at least one of a drain region and a source region by implanting impurity ions into the second ion implantation area; and
(h) a step of removing the second resist layer.
In accordance with the above-mentioned fabrication method, degradation of the gate insulation layer resulting from charges induced at the time of the ion implantation can be prevented by forming a portion of the masking resist layer with a wall extending to the gate insulation layer. Such a wall may be constituted, for example, of an opening formed in the resist layer. In other words, providing, for example, the opening in the resist layer, first, helps suppress accumulation of charges at the gate insulation layer near the gate electrode by allowing the charges built up on the surface of the resist layer to flow to the substrate through the wall constituted of the opening. Second, it helps reduce the amount of charge built up on the surface of the resist layer, which acts as a dielectric body, by lessening the resist layer area compared with the case without such opening. Consequently, the above effects can act to prevent problems associated with degradation of the gate insulation layer resulting from charge-up, such as dielectric breakdown or generation of a large number of electrically neutral electron traps in the gate insulation layer to cause the threshold voltage to be undesirably high, or lowering of the charge through the oxide Qbd to bring the tunnel oxide layer to breakdown.
The resist layer may be formed separately for every individual cells or for every individual blocks each consisting of multiple cells. When the openings for a resist layer are formed continuously in a slit-like shape, this results in a multiple number of split resist layers. Alternatively, the openings of the resist layer may be forme
Oliff & Berridg,e PLC
Seiko Epson Corporation
Trinh Michael
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