Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-01-12
2002-04-02
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S208000, C365S206000, C365S190000, C365S189040, C365S189070, C365S189090, C365S226000, C365S228000, C365S063000, C365S051000, C365S230030
Reexamination Certificate
active
06366513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuit design. More particularly, the present invention relates to improving performance by reducing noise within an integrated circuit.
Many integrated circuits or portions of integrated circuits are susceptible to noise. Virtually all circuits have a noise margin, which is the amount of noise in the circuit acceptable for the circuit to continue to function properly. Even within the noise margin, dynamic or AC performance can be degraded in the presence of noise.
One example of such a circuit is a memory integrated circuit. A memory stores data in core cells of a core cell array. Each core cell is uniquely addressable by address signals received at address input circuits. Sense amplifiers of the memory circuit detect the state of the data stored in the core cells by comparing a sensed voltage with a reference voltage. The elapsed time between presentation of an address at the address input circuits and the provision by the memory of valid data at data output circuits is the read access time.
In some very large memories, subcircuits can generate noise that affects their own operation and the operation of other circuits. For example, large memories have address input circuits which switch very fast. To speed up operation, and thereby reduce the read access time of the memory, the address input circuits are optimized for speed and switch large amounts of current. These current spikes can be coupled as noise to other subcircuits such as the sense amplifiers. Similarly, some memories that have a large number of outputs or read a large number of data bits simultaneously can switch large amounts of current during a read operation. These current spikes cause noise which can slow or interfere with operation of the sense amplifiers.
Accordingly, there is a need for a memory circuit with reduced noise and improved performance in noisy conditions.
BRIEF SUMMARY OF THE INVENTION
By way of introduction only, an integrated circuit in accordance with the present invention has separate power and ground buses supplying operating power to sensing circuits such as the sense amplifiers of a memory circuit. The power and ground buses are supplied directly from bonding pads independent of the bonding pads used for other power and ground buses of the integrated circuit. Even in an integrated circuit with many circuits switching rapidly, the sensing circuits are isolated from the switching noise.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation of the following claims, which define the scope of the invention.
REFERENCES:
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patent: 5040151 (1991-08-01), Miyawaki et al.
patent: 5666074 (1997-09-01), Chun
patent: 5970007 (1999-10-01), Shiratake
patent: 6009031 (1999-12-01), Te
Advanced Micro Devices , Inc.
Tran Andrew Q.
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