Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
2000-07-19
2002-04-09
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S355000
Reexamination Certificate
active
06369633
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a quadrature signal generation system, which is used, for example, for generating a pair of carrier signals having precise quadrature relations with each other for quadrature modulation/demodulation, image rejection frequency converter in radio communication.
FIG. 15
shows a block diagram of a prior quadrature modulator and a prior quadrature demodulator. A quadrature modulator in FIG.
15
(
a
) comprises a first analog multiplier or a double balanced-mixer (DMB)
21
a
coupled with a first baseband input (I), a second analog multiplier or a double balanced-mixer (DMB)
21
b
coupled with a second baseband input (Q), a 90° phase shifter
22
coupled with a carrier input, and an adder
23
. A quadrature demodulator in FIG.
15
(
b
) comprises a first analog multiplier or a double-balanced mixer
21
a
coupled with a first baseband output (I), a second analog multiplier or a double-balanced mixer
21
b
coupled with a second baseband output (Q), and a 90° phase shifter
22
coupled with a carrier input.
In a quadrature modulator or a quadrature demodulator, a 90° phase shifter must provide a pair of signals having precise quadrature relations, preferably phase error from 90° being less than 1° or 2°, for suppressing interference between I (in-phase) baseband signal and Q (quadrature-phase) baseband signal. Similarly, amplitude error of said pair of signals must be as small as possible, preferably, less than 1% or 2%. Further, in order to suppress an undesirable image signal (a signal separated by an IF frequency from a carrier signal in opposite direction of a desired IF signal) sufficiently in frequency conversion, further precise phase relations and precise amplitude relations (less than 1° and less than 1% for image rejection ratio higher than 40 dB) are requested.
FIG. 16
shows a basic block diagram of a prior image rejection receiver, which comprises analog multipliers or double balanced-mixers
21
a,
21
b
coupled with an RF input, 90° phase shifters
22
a
and
22
b,
and an adder
23
.
FIG. 17
is a circuit diagram of a prior 90° phase shifter using a low pass filter and a high pass filter, and
FIG. 18
shows characteristics of a prior low pass filter and a prior high pass filter shown in FIG.
17
. As a 90° phase shifter for carrier signals, an RC/CR type phase shifter as shown in
FIG. 17
is popularly used. In
FIG. 17
, numeral
31
is an RC type low pass filter, and numeral
32
is a CR type high pass filter. In
FIG. 18
, 90° phase difference is kept in whole frequency, and amplitude error is zero at the frequency where &ohgr;RC=1 is satisfied.
FIG. 19
is another prior phase shifter using one stage poly phase filter constituted by a capacitor C and a resistor R. In
FIG. 19
, when a pair of differential inputs having phase difference of 180° are applied to input terminals In+and In−, output terminals I+, Q+, I− and I+ provide phases 0°, 90°, 180° and 270°, respectively. Therefore, for instance by taking I+ and Q+, a 90° phase shifter is obtained.
FIG. 20
shows frequency characteristics of phase and amplitude of a phase shifter of FIG.
19
. As shown in
FIG. 20
, the frequency characteristics are flat irrespective of frequency, however, 90° phase relation is satisfied only at the frequency f (=&ohgr;/2&pgr;) (&ohgr;RC=1).
However, the prior arts mentioned above have the disadvantage that phase error is inevitable due to an error of a capacitor and/or a resistor when a circuit is provided by an integrated circuit (IC). That phase error decreases a yield rate of an IC itself. In practice, a phase error around 2° or 3° is inevitable, however, that phase error is not satisfactory for multi-level quadrature modulation such as 16 QAM. In particular, that phase error can not provide an excellent image rejection frequency converter.
In a direct conversion system in which modulation/demodulation is carried out directly at RF frequency, quadrature frequencies are as high as GHz order, and therefore, phase error would be further increased caused by a parasitic effect.
Thus, a prior 90° phase shifter has the disadvantage that a precise 90° phase shifter operating in high frequency is impossible due to an error of components, and/or a parasitic effect.
SUMMARY OF THE INVENTION
It is an object, therefore, to provide a new and improved quadrature signal generation system by overcoming the disadvantages and limitations of a prior quadrature signal generation system.
It is also an object of the present invention to provide a quadrature signal generation system which can operate satisfactory in spite of an error of a component in high frequency.
The above and other objects are attained by a quadrature signal generation system comprising; a pair of input terminals receiving a first A.C. signal and a second A.C. signal, each having a predetermined frequency and phase relation of approximate 90° with each other; a multiplier circuit for providing a product of said first A.C. signal and said second A.C. signal, said product being called a third A.C. signal; a square-difference circuit for providing a difference of a square of the first A.C. signal and a square of the second A.C. signal, said difference called a fourth A.C. signal; the frequency of said third A.C. signal and said fourth A.C. signal being equal to twice of frequency of said first A.C. signal and said second A.C. signal, and said third A.C. signal and said fourth A.C. signal having fine phase relation of 90° with each other.
Preferably, a 6 dB amplifier coupled with an output of said multiplier is provided.
Preferably, a pair of 3 dB amplifiers coupled with each inputs of said multiplier are provided.
Still preferably, said multiplier is implemented by using a Gilbert cell type transistor circuit.
Still preferably, said square-difference circuit comprises an adder for providing a sum of said first A.C. signal and said second A.C. signal, a subtractor for providing a difference between said first A.C. signal and said second A.C. signal, and a second multiplier for providing a product of an output of said adder and said subtractor.
Still preferably, said multiplier comprises an adder for providing a sum of said first A.C. signal and said second A.C. signal, a subtractor for providing a difference between said first A.C. signal and said second A.C. signal, a second square-difference circuit for providing a difference between a square of an output of said adder and a square of an output of said subtractor.
Still preferably, a series circuit of a capacitor and a limiter amplifier is provided at an output of said multiplier and an output of said square-difference circuit.
Still preferably, a phase shifter is provided for accepting an input signal having a predetermined frequency and providing said first A.C. signal and said second A.C. signal having phase relation of 90° with each other.
The present invention further provides a method for generating signals having quadrature phase relation with each other comprising the steps of; multiplying a first A.C. signal and a second A.C. signal each having a predetermined frequency and having phase relation of approximate 90° with each other, and providing a third A.C. signal; and providing a difference between a square of said first A.C. signal and a square of said second A.C. signal, as a fourth A.C. signal which has the same frequency as that of the third A.C. signal, and the phase relation of 90° from that of the third A.C. signal.
REFERENCES:
patent: 4379266 (1983-04-01), Rubin
patent: 4431969 (1984-02-01), Summers et al.
patent: 5063446 (1991-11-01), Gibson
patent: 5121057 (1992-06-01), Huber et al.
patent: 5412351 (1995-05-01), Nystrom et al.
patent: 6031865 (2000-02-01), Kelton et al.
patent: 6151313 (2000-11-01), Abramson
patent: 6181181 (2001-01-01), Tsukahara et al.
Tsukahara et al., ISSCC 2000 Session 23 Wireless Building Blocks Paper WP23.5, Feb. 9, 2000, pp. 384-385, p. 471, pp. 310-311, pp. 501.
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