Method of making three dimensional, 2R memory having a 4F2...

Details Method of making three dimensional, 2R memory having a 4F2... Method of making three dimensional, 2R memory having a 4F2...

2008-06-03

2008-06-03

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE21665, C438S295000

Reexamination Certificate

active

07381616

ABSTRACT:
A method of fabricating a multi-level 3D memory array includes: preparing a wafer and peripheral circuits thereon; layers of metal, memory resistor material, and metal are deposited, patterned and etched. The steps of the method of the invention are repeated for N levels of a memory array.

REFERENCES:
patent: 7009278 (2006-03-01), Hsu
patent: 7236389 (2007-06-01), Hsu
patent: 7291878 (2007-11-01), Stipe
patent: 2007/0132049 (2007-06-01), Stipe

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