Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

2008-05-13

2008-05-13

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C257SE27057

Reexamination Certificate

active

07371644

ABSTRACT:
According to the present invention, there is provided a semiconductor device fabrication method, comprising:depositing a mask material on a semiconductor substrate;patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region;burying a device isolation insulating film in the trench;etching away a predetermined amount of the device isolation insulating film formed in the first region;etching away the mask material formed in the second region;forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection;depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film;planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region;depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; andpatterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.

REFERENCES:
patent: 6911383 (2005-06-01), Doris et al.
patent: 7250658 (2007-07-01), Doris et al.
patent: 2004/0061178 (2004-04-01), Lin et al.
patent: 1591838 (2005-03-01), None
patent: 2005-19996 (2005-01-01), None
Notification of the First Office Action issued by the Chinese Patent Office on Sep. 14, 2007, for Chinese Patent Application No. 200610088529.9, and English-language translation thereof.
Choi, et al., “A Spacer Patterning Technology for Nanoscale CMOS,” IEEE Transactions on Electron Devices, vol. 49, No. 3, pp. 436-441, Mar. 2002.

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